| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-11-13 | Route cpu_rst_n signal through bus master | Alejandro Soto |
| 2022-11-10 | Fix reset glitches | Alejandro Soto |
| 2022-11-09 | Implement reset | Alejandro Soto |
| 2022-11-09 | Add reset signal to bus master | Alejandro Soto |
| 2022-11-09 | Fix bus protocol errors in bus master | Alejandro Soto |
| 2022-11-08 | Fix handling of multi-cycle Avalon waitrequest states in bus master | Alejandro Soto |
| 2022-11-02 | Add bus master forward signals: irq, cpu_clk | Alejandro Soto |
| 2022-11-02 | Move bus/master.sv to bus_master.sv | Alejandro Soto |
| 2022-10-15 | Rework bus architecture | Alejandro Soto |
| 2022-09-18 | Rename data_rw to data_wr in bus master | Alejandro Soto |
| 2022-09-18 | Fix memory simulation | Alejandro Soto |
| 2022-09-17 | Update project structure to match Verilator Makefile | Alejandro Soto |
| 2022-09-04 | Add Avalon bus master | Alejandro Soto |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |