| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-04-27 | rtl/axi_timer: initial commit | Alejandro Soto | |
| This a buggy timer, imported from https://github.com/astrakhov-design/axi_timer. It will be used for a testbench hello world case | |||
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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