| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-10-15 | Rework bus architecture | Alejandro Soto |
| 2022-09-23 | Remap top 512MiB of HPS DDR3 | Alejandro Soto |
| 2022-09-19 | DDR3 is working | Alejandro Soto |
| 2022-09-04 | Add Avalon bus master | Alejandro Soto |
| 2022-09-02 | Add hps_0 platform design | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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