| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-03-09 | mk/verilator: add output line to sim | Alejandro Soto | |
| 2024-03-03 | rtl: add dma_axi32 | Alejandro Soto | |
| 2024-02-20 | mk: implement support for quartus synthesis | Alejandro Soto | |
| 2024-02-20 | mk: add enable_prof flag for verilator | Alejandro Soto | |
| 2024-02-20 | mk: initial commit | Alejandro Soto | |
| This is a complete overhaul of the build system. This new implementations upports many new features and is very extensible. | |||
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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