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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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2024-05-24
mk/cc: implement ld_extra
Alejandro Soto
2024-05-24
mk/verilator: set timescale
Alejandro Soto
2024-05-24
mk/cc: generate cc header dependency files
Alejandro Soto
2024-05-24
mk: implement support for meson, ninja
Alejandro Soto
2024-05-24
mk: implement support for cc, objcopy
Alejandro Soto
2024-05-24
scripts/makehex: initial commit
Alejandro Soto
2024-05-24
mk/obj: initial commit
Alejandro Soto
2024-05-24
mk/verilator: pass -march=native on enable=opt
Alejandro Soto
2024-05-24
mk/verilator: add cpp sources as make dependencies of Vtop
Alejandro Soto
2024-05-24
mk/cores: add context to unknown_core
Alejandro Soto
2024-05-24
mk/cocotb: run cocotb even if results.xml is up-to-date
Alejandro Soto
2024-05-24
mk/quartus: scan each core's rtl_dirs
Alejandro Soto
2024-05-05
mk: support verbose cocotb output
Alejandro Soto
2024-04-27
mk: implement peakrdl support
Alejandro Soto
2024-03-09
mk/verilator: add output line to sim
Alejandro Soto
2024-03-03
rtl: add dma_axi32
Alejandro Soto
2024-02-20
mk: implement support for quartus synthesis
Alejandro Soto
2024-02-20
mk: add enable_prof flag for verilator
Alejandro Soto
2024-02-20
mk: initial commit
Alejandro Soto
This is a complete overhaul of the build system. This new implementations upports many new features and is very extensible.