| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-10-26 | rtl/gfx: synchronize clock with SDRAM | Alejandro Soto | |
| 2023-10-21 | ip: downgrade to 16-bit floats | Alejandro Soto | |
| 2023-10-20 | ip: add ip_fp_add, ip_fp_mul | Alejandro Soto | |
| 2022-11-06 | Add dsp_mul IP variation | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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