| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-09-25 | Makefile: enable multithreaded verilated models | Alejandro Soto | |
| 2023-09-24 | sim: fix silent fopen() fail | Alejandro Soto | |
| 2022-12-06 | Implement gdbstub | Alejandro Soto | |
| 2022-11-09 | Implement initial state randomization in sim | Alejandro Soto | |
| 2022-10-23 | Verilate with max optimization level | Alejandro Soto | |
| 2022-10-23 | Compile sim tests with debug info | Alejandro Soto | |
| 2022-10-16 | Implement register dumps | Alejandro Soto | |
| 2022-10-16 | Add C simulation testbench | Alejandro Soto | |
| 2022-10-16 | Implement simulation testbenches | Alejandro Soto | |
| 2022-09-17 | Update project structure to match Verilator Makefile | Alejandro Soto | |
| 2022-09-01 | Initial commit | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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