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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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2023-10-04
sim: implement fst traces
Alejandro Soto
2023-10-04
sim: implement flag overrides in environment
Alejandro Soto
2023-10-04
Makefile: replace DISABLE_THREADS with ENABLE_THREADS
Alejandro Soto
2023-10-04
Makefile: implement dist
Alejandro Soto
2023-10-04
Makefile: add %.bin to .PRECIOUS
Alejandro Soto
2023-10-04
Makefile: add rules for demo
Alejandro Soto
2023-10-03
Makefile: disable lto for debug builds
Alejandro Soto
2023-10-01
Makefile: set proper paths for linux boot
Alejandro Soto
2023-09-29
tb: enable sim performance flags ("faster is better")
Alejandro Soto
2023-09-26
Makefile: add $(COV_DIR) to clean target
Alejandro Soto
2023-09-25
tb: implement coverage reports
Alejandro Soto
2023-09-25
Makefile: enable multithreaded verilated models
Alejandro Soto
2023-09-24
sim: fix silent fopen() fail
Alejandro Soto
2022-12-06
Implement gdbstub
Alejandro Soto
2022-11-09
Implement initial state randomization in sim
Alejandro Soto
2022-10-23
Verilate with max optimization level
Alejandro Soto
2022-10-23
Compile sim tests with debug info
Alejandro Soto
2022-10-16
Implement register dumps
Alejandro Soto
2022-10-16
Add C simulation testbench
Alejandro Soto
2022-10-16
Implement simulation testbenches
Alejandro Soto
2022-09-17
Update project structure to match Verilator Makefile
Alejandro Soto