conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2022-10-25	mul: identar con tabs en lugar de espacios	fabian-mv
2022-10-25	mul: pasa a usar tipos definidos en uarch	fabian-mv
2022-10-25	mul: actualiza API de modulo de multiplicación	fabian-mv
2022-10-25	Implement explicit sim state dump	Alejandro Soto
2022-10-25	Add sim test: tarea2	Alejandro Soto
2022-10-25	Split mux logic out of control.sv	Alejandro Soto
2022-10-24	Split cycle logic out of control.sv	Alejandro Soto
2022-10-24	Split stall control logic out of control.sv	Alejandro Soto
2022-10-23	Move control cycles enum to public uarch interface	Alejandro Soto
2022-10-23	Pack general control signals as struct datapath_decode	Alejandro Soto
2022-10-23	Move signal `uses_rn` to struct data_decode	Alejandro Soto
2022-10-23	Move branch control signals to struct branch_decode	Alejandro Soto
2022-10-23	Enforce UND exceptions when SBZ is not followed in data-processing instructions	Alejandro Soto
2022-10-23	Document U-Boot porting	Alejandro Soto
2022-10-23	Verilate with max optimization level	Alejandro Soto
2022-10-23	Compile sim tests with debug info	Alejandro Soto
2022-10-23	Add sim test: shifts	Alejandro Soto
2022-10-23	Fix PC writeback hazard	Alejandro Soto
2022-10-23	Add sim test: stack	Alejandro Soto
2022-10-23	Fix ldm writeback	Alejandro Soto
2022-10-23	Fix zero-extended (lsr) vs sign-extended (asr) shifts	Alejandro Soto
2022-10-23	añade sugerencias y TODO	Fabián Montero
2022-10-23	Fix bad decoding of second-operand immediates	Alejandro Soto
2022-10-20	mul: arregla typos	fabian-mv
2022-10-19	mul: añade base para instrucción MUL	Fabián Montero
2022-10-18	Add sim test: control_flow	Alejandro Soto
2022-10-18	Implement branch with link	Alejandro Soto
2022-10-18	Add sim test: mult	Alejandro Soto
2022-10-18	Print simulator command line on test failure	Alejandro Soto
2022-10-18	Support skipping tests	Alejandro Soto
2022-10-18	Support program counter in --dump-regs	Alejandro Soto
2022-10-18	Implement undefined instruction exceptions	Alejandro Soto
2022-10-18	Implement register initialization in sim	Alejandro Soto
2022-10-17	Break sub-100MHz critical path involving wb_alu_flags	Alejandro Soto
2022-10-17	Add instruction list	Alejandro Soto
2022-10-17	Move pitfalls.txt to doc/	Alejandro Soto
2022-10-17	Add LICENSE	Alejandro Soto
2022-10-17	Break false dependency on r0 for MOV/MVN	Alejandro Soto
2022-10-17	Use negative clock edge for register file in Verilator builds	Alejandro Soto
2022-10-17	Fix unsafe decode signals	Alejandro Soto
2022-10-17	Improve sim.py output	Alejandro Soto
2022-10-17	Fix data hazards in nzcv and PC increment	Alejandro Soto
2022-10-16	Implement register dumps	Alejandro Soto
2022-10-16	Add C simulation testbench	Alejandro Soto
2022-10-16	Add original simulation testbench	Alejandro Soto
2022-10-16	Add flake.nix	Alejandro Soto
2022-10-16	Implement simulation testbenches	Alejandro Soto
2022-10-16	Rename cycles as control	Alejandro Soto
2022-10-16	Move isa.sv to core/decode	Alejandro Soto
2022-10-16	Set core clock target to 100MHz	Alejandro Soto