conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2022-10-17	Fix unsafe decode signals	Alejandro Soto
2022-10-17	Improve sim.py output	Alejandro Soto
2022-10-17	Fix data hazards in nzcv and PC increment	Alejandro Soto
2022-10-16	Implement register dumps	Alejandro Soto
2022-10-16	Add C simulation testbench	Alejandro Soto
2022-10-16	Add original simulation testbench	Alejandro Soto
2022-10-16	Add flake.nix	Alejandro Soto
2022-10-16	Implement simulation testbenches	Alejandro Soto
2022-10-16	Rename cycles as control	Alejandro Soto
2022-10-16	Move isa.sv to core/decode	Alejandro Soto
2022-10-16	Set core clock target to 100MHz	Alejandro Soto
2022-10-15	Fix flags and writeback hazards	Alejandro Soto
2022-10-15	Fix branch target calculation	Alejandro Soto
2022-10-15	Rework bus architecture	Alejandro Soto
2022-10-09	Implement most memory transactions	Alejandro Soto
2022-10-09	Pipeline flags writeback (breaks combinational data dependencies)	Alejandro Soto
2022-10-08	Fix writes to PC	Alejandro Soto
2022-10-08	Implement LDR/STR decode	Alejandro Soto
2022-10-08	Rename EXECUTE cycle as ISSUE	Alejandro Soto
2022-10-03	Fix pipeline hazards	Alejandro Soto
2022-10-02	Split decoding of flexible second operand out of data instructions	Alejandro Soto
2022-10-02	Make the fetch stage use the bus arbiter	Alejandro Soto
2022-10-02	Add MMU bus arbiter	Alejandro Soto
2022-10-02	Use @(posedge clk) in register files	Alejandro Soto
2022-10-02	Major shifter-ALU redesign	Alejandro Soto
2022-09-27	Switch from operand forwarding to next insn stalls (improves Fmax)	Alejandro Soto
2022-09-27	Fix branching bugs	Alejandro Soto
2022-09-27	Add simple loop execution testbench	Alejandro Soto
2022-09-27	Implement branching in fetch stage	Alejandro Soto
2022-09-26	Fix MVN (not instead of neg)	Alejandro Soto
2022-09-26	Fix writeback timing	Alejandro Soto
2022-09-26	Fix prefetch PC not advancing when buffer is empty	Alejandro Soto
2022-09-26	Fix shifter addressing modes	Alejandro Soto
2022-09-26	Implement ALU shifter	Alejandro Soto
2022-09-25	Define ALU control signal set	Alejandro Soto
2022-09-25	Implement shifter decoding	Alejandro Soto
2022-09-25	Rename HPS SDRAM testbench file	Alejandro Soto
2022-09-25	Shorten decode_* nets to dec_*	Alejandro Soto
2022-09-25	Implement flag updates	Alejandro Soto
2022-09-25	Refactor CPSR and uarch.sv	Alejandro Soto
2022-09-25	Fix Quartus issues	Alejandro Soto
2022-09-25	Implement PSR flag handling	Alejandro Soto
2022-09-25	Implement ALU opcode decoding	Alejandro Soto
2022-09-25	Implement ALU	Alejandro Soto
2022-09-25	Implement initial cycle control logic	Alejandro Soto
2022-09-25	Add fetch jump target	Alejandro Soto
2022-09-25	Fetch NOP on prefetch flush	Alejandro Soto
2022-09-25	Implement branch handling in decode	Alejandro Soto
2022-09-25	Use word/ptr instead of logic[..]	Alejandro Soto
2022-09-25	Implement register file	Alejandro Soto