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AgeCommit message (Expand)Author
2022-10-29doc: añade manual de ARM, investigación y diagrama de bloquesFabián Montero
2022-10-25Add missing nativeBuildInputs to flake.nixAlejandro Soto
2022-10-25Move flake.nix to nix/ subdirectoryAlejandro Soto
2022-10-25Implement explicit sim state dumpAlejandro Soto
2022-10-25Add sim test: tarea2Alejandro Soto
2022-10-25Split mux logic out of control.svAlejandro Soto
2022-10-24Split cycle logic out of control.svAlejandro Soto
2022-10-24Split stall control logic out of control.svAlejandro Soto
2022-10-23Move control cycles enum to public uarch interfaceAlejandro Soto
2022-10-23Pack general control signals as struct datapath_decodeAlejandro Soto
2022-10-23Move signal `uses_rn` to struct data_decodeAlejandro Soto
2022-10-23Move branch control signals to struct branch_decodeAlejandro Soto
2022-10-23Enforce UND exceptions when SBZ is not followed in data-processing instructionsAlejandro Soto
2022-10-23Document U-Boot portingAlejandro Soto
2022-10-23Verilate with max optimization levelAlejandro Soto
2022-10-23Compile sim tests with debug infoAlejandro Soto
2022-10-23Add sim test: shiftsAlejandro Soto
2022-10-23Fix PC writeback hazardAlejandro Soto
2022-10-23Add sim test: stackAlejandro Soto
2022-10-23Fix ldm writebackAlejandro Soto
2022-10-23Fix zero-extended (lsr) vs sign-extended (asr) shiftsAlejandro Soto
2022-10-23Fix bad decoding of second-operand immediatesAlejandro Soto
2022-10-18Add sim test: control_flowAlejandro Soto
2022-10-18Implement branch with linkAlejandro Soto
2022-10-18Add sim test: multAlejandro Soto
2022-10-18Print simulator command line on test failureAlejandro Soto
2022-10-18Support skipping testsAlejandro Soto
2022-10-18Support program counter in --dump-regsAlejandro Soto
2022-10-18Implement undefined instruction exceptionsAlejandro Soto
2022-10-18Implement register initialization in simAlejandro Soto
2022-10-17Break sub-100MHz critical path involving wb_alu_flagsAlejandro Soto
2022-10-17Add instruction listAlejandro Soto
2022-10-17Move pitfalls.txt to doc/Alejandro Soto
2022-10-17Add LICENSEAlejandro Soto
2022-10-17Break false dependency on r0 for MOV/MVNAlejandro Soto
2022-10-17Use negative clock edge for register file in Verilator buildsAlejandro Soto
2022-10-17Fix unsafe decode signalsAlejandro Soto
2022-10-17Improve sim.py outputAlejandro Soto
2022-10-17Fix data hazards in nzcv and PC incrementAlejandro Soto
2022-10-16Implement register dumpsAlejandro Soto
2022-10-16Add C simulation testbenchAlejandro Soto
2022-10-16Add original simulation testbenchAlejandro Soto
2022-10-16Add flake.nixAlejandro Soto
2022-10-16Implement simulation testbenchesAlejandro Soto
2022-10-16Rename cycles as controlAlejandro Soto
2022-10-16Move isa.sv to core/decodeAlejandro Soto
2022-10-16Set core clock target to 100MHzAlejandro Soto
2022-10-15Fix flags and writeback hazardsAlejandro Soto
2022-10-15Fix branch target calculationAlejandro Soto
2022-10-15Rework bus architectureAlejandro Soto
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