summaryrefslogtreecommitdiff
path: root/tb
diff options
context:
space:
mode:
Diffstat (limited to '')
-rw-r--r--tb/__init__.py0
-rw-r--r--tb/top/__init__.py0
-rw-r--r--tb/top/conspiracion.cpp84
-rw-r--r--tb/top/conspiracion/args.hxx (renamed from tb/args.hxx)0
-rw-r--r--tb/top/conspiracion/platform.sv (renamed from tb/platform.sv)0
-rw-r--r--tb/top/conspiracion/sim_slave.cpp (renamed from tb/sim_slave.cpp)0
-rw-r--r--tb/top/conspiracion/sim_slave.hpp (renamed from tb/sim_slave.hpp)4
-rw-r--r--tb/top/conspiracion/sim_slave.sv (renamed from tb/sim_slave.sv)0
-rw-r--r--tb/top/conspiracion/vga_domain.sv (renamed from tb/vga_domain.sv)0
-rw-r--r--tb/top/decode_test.cpp101
-rw-r--r--tb/top/fetch_test.cpp166
-rw-r--r--tb/top/hps_sdram_test.cpp93
-rw-r--r--tb/top/mul_test.cpp71
-rw-r--r--tb/top/smp_sim.cpp0
-rw-r--r--tb/top/smp_sim.py0
15 files changed, 44 insertions, 475 deletions
diff --git a/tb/__init__.py b/tb/__init__.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tb/__init__.py
diff --git a/tb/top/__init__.py b/tb/top/__init__.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tb/top/__init__.py
diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp
index a0de8f4..198cc30 100644
--- a/tb/top/conspiracion.cpp
+++ b/tb/top/conspiracion.cpp
@@ -16,41 +16,41 @@
#include <verilated_fst_c.h>
#endif
-#include "Vconspiracion.h"
-#include "Vconspiracion_arm810.h"
-#include "Vconspiracion_conspiracion.h"
-#include "Vconspiracion_platform.h"
-#include "Vconspiracion_sim_slave.h"
-#include "Vconspiracion_vga_domain.h"
-#include "Vconspiracion_core.h"
-#include "Vconspiracion_core_control.h"
-#include "Vconspiracion_core_control_issue.h"
-#include "Vconspiracion_core_cp15_domain.h"
-#include "Vconspiracion_core_cp15_far.h"
-#include "Vconspiracion_core_cp15_fsr.h"
-#include "Vconspiracion_core_cp15_syscfg.h"
-#include "Vconspiracion_core_cp15_ttbr.h"
-#include "Vconspiracion_core_cp15.h"
-#include "Vconspiracion_core_fetch.h"
-#include "Vconspiracion_core_mmu.h"
-#include "Vconspiracion_core_psr.h"
-#include "Vconspiracion_core_regs.h"
-#include "Vconspiracion_core_reg_file.h"
-#include "Vconspiracion_cache.h"
-#include "Vconspiracion_cache__T1.h"
-#include "Vconspiracion_cache_sram.h"
-
-#include "../args.hxx"
-
-#include "../avalon.hpp"
-#include "../const.hpp"
-#include "../mem.hpp"
-#include "../jtag_uart.hpp"
-#include "../interval_timer.hpp"
-#include "../null.hpp"
-#include "../sim_slave.hpp"
-#include "../window.hpp"
-#include "../vga.hpp"
+#include "Vtop.h"
+#include "Vtop_arm810.h"
+#include "Vtop_conspiracion.h"
+#include "Vtop_platform.h"
+#include "Vtop_sim_slave.h"
+#include "Vtop_vga_domain.h"
+#include "Vtop_core.h"
+#include "Vtop_core_control.h"
+#include "Vtop_core_control_issue.h"
+#include "Vtop_core_cp15_domain.h"
+#include "Vtop_core_cp15_far.h"
+#include "Vtop_core_cp15_fsr.h"
+#include "Vtop_core_cp15_syscfg.h"
+#include "Vtop_core_cp15_ttbr.h"
+#include "Vtop_core_cp15.h"
+#include "Vtop_core_fetch.h"
+#include "Vtop_core_mmu.h"
+#include "Vtop_core_psr.h"
+#include "Vtop_core_regs.h"
+#include "Vtop_core_reg_file.h"
+#include "Vtop_cache.h"
+#include "Vtop_cache__T1.h"
+#include "Vtop_cache_sram.h"
+
+#include "args.hxx"
+
+#include "avalon.hpp"
+#include "const.hpp"
+#include "mem.hpp"
+#include "jtag_uart.hpp"
+#include "interval_timer.hpp"
+#include "null.hpp"
+#include "sim_slave.hpp"
+#include "window.hpp"
+#include "vga.hpp"
namespace
{
@@ -307,7 +307,7 @@ int main(int argc, char **argv)
dup2(*control_fd, STDERR_FILENO);
}
- Vconspiracion top;
+ Vtop top;
#if VM_TRACE
VerilatedFstC trace;
@@ -335,8 +335,8 @@ int main(int argc, char **argv)
null vram_null(0x3800'0000, 64 << 20, 2);
window vram_window(vram, 0x0000'0000);
- Vconspiracion_platform &plat = *top.conspiracion->plat;
- display<Vconspiracion_vga_domain> vga
+ Vtop_platform &plat = *top.conspiracion->plat;
+ display<Vtop_vga_domain> vga
(
*plat.vga, 0x3800'0000, 25'175'000, 50'000'000
);
@@ -347,8 +347,8 @@ int main(int argc, char **argv)
sim_slave dbg_3(*plat.smp_dbg_3, 0x3013'0000, 32);
sim_slave smp_ctrl(*plat.smp_sim, 0x3014'0000, 4);
- interconnect<Vconspiracion_platform> avl(plat);
- //interconnect<Vconspiracion_vga_domain> avl_vga(plat->vga);
+ interconnect<Vtop_platform> avl(plat);
+ //interconnect<Vtop_vga_domain> avl_vga(plat->vga);
std::vector<const_map> consts;
for(const auto &init : *const_)
@@ -411,14 +411,14 @@ int main(int argc, char **argv)
std::fclose(img_file);
}
- Vconspiracion_arm810 *const cores[] = {
+ Vtop_arm810 *const cores[] = {
plat.cpu_0->cpu,
plat.cpu_1->cpu,
plat.cpu_2->cpu,
plat.cpu_3->cpu
};
- Vconspiracion_cache_sram *const caches[] = {
+ Vtop_cache_sram *const caches[] = {
plat.cache_0->sram,
plat.cache_1->sram,
plat.cache_2->sram,
diff --git a/tb/args.hxx b/tb/top/conspiracion/args.hxx
index 69ccbf6..69ccbf6 100644
--- a/tb/args.hxx
+++ b/tb/top/conspiracion/args.hxx
diff --git a/tb/platform.sv b/tb/top/conspiracion/platform.sv
index bbf1088..bbf1088 100644
--- a/tb/platform.sv
+++ b/tb/top/conspiracion/platform.sv
diff --git a/tb/sim_slave.cpp b/tb/top/conspiracion/sim_slave.cpp
index 24528d2..24528d2 100644
--- a/tb/sim_slave.cpp
+++ b/tb/top/conspiracion/sim_slave.cpp
diff --git a/tb/sim_slave.hpp b/tb/top/conspiracion/sim_slave.hpp
index cdcea78..12cec62 100644
--- a/tb/sim_slave.hpp
+++ b/tb/top/conspiracion/sim_slave.hpp
@@ -3,13 +3,13 @@
#include <cstdint>
-#include "Vconspiracion_sim_slave.h"
+#include "Vtop_sim_slave.h"
#include "avalon.hpp"
namespace taller::avalon
{
- using verilated_slave = Vconspiracion_sim_slave;
+ using verilated_slave = Vtop_sim_slave;
class sim_slave : public slave
{
diff --git a/tb/sim_slave.sv b/tb/top/conspiracion/sim_slave.sv
index 1598701..1598701 100644
--- a/tb/sim_slave.sv
+++ b/tb/top/conspiracion/sim_slave.sv
diff --git a/tb/vga_domain.sv b/tb/top/conspiracion/vga_domain.sv
index 0c9aac5..0c9aac5 100644
--- a/tb/vga_domain.sv
+++ b/tb/top/conspiracion/vga_domain.sv
diff --git a/tb/top/decode_test.cpp b/tb/top/decode_test.cpp
deleted file mode 100644
index 4b78535..0000000
--- a/tb/top/decode_test.cpp
+++ /dev/null
@@ -1,101 +0,0 @@
-#include <cstdio>
-
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-
-#include "Vdecode_test.h" // From Verilating "top.v"
-
-int main(int argc, char** argv) {
- Verilated::commandArgs(argc, argv); // Remember args
- Verilated::traceEverOn(true);
-
- Vdecode_test top;
- VerilatedVcdC trace;
-
- top.trace(&trace, 0);
- trace.open("decode_test.vcd");
-
- // sim/control_flow.c
- uint32_t rom[] =
- {
- 0xea000032,
- 0xea000034,
- 0xea000000,
- 0xeafffffe,
- 0xeafffffe,
- 0xeafffffe,
- 0xeafffffe,
- 0xe3500000,
- 0xda000001,
- 0xe3a00001,
- 0xe1a0f00e,
- 0x13e00000,
- 0x03a00000,
- 0xe1a0f00e,
- 0xe1a02000,
- 0xe92d4010,
- 0xe1a00002,
- 0xebfffff4,
- 0xe1a03000,
- 0xe1a00001,
- 0xebfffff1,
- 0xe0933000,
- 0x0a00000c,
- 0xe3730001,
- 0x0a00000e,
- 0xe3530001,
- 0x0a00000a,
- 0xe1a038a1,
- 0xe1a00502,
- 0xe1833601,
- 0xe02023c2,
- 0xe0831001,
- 0xe1520001,
- 0xcaffffed,
- 0xe0820001,
- 0xe8bd8010,
- 0xe1a02822,
- 0xe1822801,
- 0xe1a00f62,
- 0xe8bd8010,
- 0xe3500000,
- 0xda000002,
- 0xe1a02001,
- 0xe2611001,
- 0xeafffff2,
- 0xe1e02001,
- 0xe1a00002,
- 0xebffffd6,
- 0xe3500000,
- 0xdaffffed,
- 0xe1a01002,
- 0xeafffff5,
- 0xe59fd008,
- 0xebffffd7,
- 0xeafffffe,
- 0xeafffffe,
- 0x20000000,
- };
-
- int clk_tick = 0;
- int time = 0;
-
- for(int i = 0; i < sizeof(rom)/sizeof(rom[0]); ++i)
- {
- top.insn = rom[i];
-
- top.eval();
- trace.dump(time++);
-
- std::printf("insn=0x%08x, dec=0x", top.insn);
- for(std::size_t j = 0; j < sizeof(top.dec) / sizeof(top.dec[0]); ++j)
- {
- std::printf("%08x", top.dec[j]);
- }
-
- std::puts("");
- }
-
- trace.close();
- top.final(); // Done simulating
-}
diff --git a/tb/top/fetch_test.cpp b/tb/top/fetch_test.cpp
deleted file mode 100644
index 06768c4..0000000
--- a/tb/top/fetch_test.cpp
+++ /dev/null
@@ -1,166 +0,0 @@
-#include <cstdio>
-
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-
-#include "Vfetch_test.h" // From Verilating "top.v"
-
-int main(int argc, char** argv) {
- Verilated::commandArgs(argc, argv); // Remember args
- Verilated::traceEverOn(true);
-
- Vfetch_test top;
- VerilatedVcdC trace;
-
- top.trace(&trace, 0);
- trace.open("fetch_test.vcd");
-
- top.clk = 0;
- top.stall = 0; //insn y insn_pc se detienen
- top.branch = 0; //forma de flush -> instr saltan a la instr de la branch
- top.prefetch_flush = 0; //limpia prefetch
- top.fetched = 1; //estado del fetch (ready)
- top.wr_pc = 0; //cuando hay un write al pc
- top.branch_target = 0; //direccion a la que se hace salto
- top.wr_current = 0; //ultimo que se guardo en registros
- top.fetch_data = 0x00000000; //data que se leyó al hacer fetch
-
- uint32_t rom[] =
- {
- 0xea000032,
- 0xea000034,
- 0xea000000,
- 0xeafffffe,
- 0xeafffffe,
- 0xeafffffe,
- 0xeafffffe,
- 0xe3500000,
- 0xda000001,
- 0xe3a00001,
- 0xe1a0f00e,
- 0x13e00000,
- 0x03a00000,
- 0xe1a0f00e,
- 0xe1a02000,
- 0xe92d4010,
- 0xe1a00002,
- 0xebfffff4,
- 0xe1a03000,
- 0xe1a00001,
- 0xebfffff1,
- 0xe0933000,
- 0x0a00000c,
- 0xe3730001,
- 0x0a00000e,
- 0xe3530001,
- 0x0a00000a,
- 0xe1a038a1,
- 0xe1a00502,
- 0xe1833601,
- 0xe02023c2,
- 0xe0831001,
- 0xe1520001,
- 0xcaffffed,
- 0xe0820001,
- 0xe8bd8010,
- 0xe1a02822,
- 0xe1822801,
- 0xe1a00f62,
- 0xe8bd8010,
- 0xe3500000,
- 0xda000002,
- 0xe1a02001,
- 0xe2611001,
- 0xeafffff2,
- 0xe1e02001,
- 0xe1a00002,
- 0xebffffd6,
- 0xe3500000,
- 0xdaffffed,
- 0xe1a01002,
- 0xeafffff5,
- 0xe59fd008,
- 0xebffffd7,
- 0xeafffffe,
- 0xeafffffe,
- 0x20000000,
- };
-
- int clk_tick = 0;
- int time = 0;
-
- std::printf("CPU cycle:\n");
- while (time < 50)
- {
- top.eval();
- trace.dump(time++);
-
- if(!top.clk)
- {
- std::printf("insn=0x%08x, insn_pc=0x%08x, addr=0x%08x\n",
- top.insn, top.insn_pc, top.addr);
- }
-
- top.clk = !top.clk;
-
- top.fetch_data = rom[top.addr];
- }
-
- std::printf("Branch, flush, stall:\n");
- while (time < 99)
- {
- top.eval();
- trace.dump(time++);
-
- if(!top.clk)
- {
- std::printf("insn=0x%08x, insn_pc=0x%08x, addr=0x%08x\n",
- top.insn, top.insn_pc, top.addr);
- }
-
- top.clk = !top.clk;
-
- if(time == 55)
- {
- std::printf("Se hace un branch:\n");
- top.branch = 1;
- top.branch_target = 3;
- }
-
- if(time == 59)
- {
- std::printf("Se termina el branch:\n");
- top.branch = 0;
-
- }
-
- if(time == 63){
- std::printf("Se hace un flush:\n");
- top.branch = 0;
- top.branch_target = 0;
- top.prefetch_flush = 1;
- }
-
- if(time == 69){
- std::printf("Se termina el flush:\n");
- top.prefetch_flush = 0;
- }
-
- if(time == 75)
- {
- std::printf("Se hace un stall:\n");
- top.stall = 1;
- }
-
- if(time == 81)
- {
- std::printf("Se termina el stall:\n");
- top.stall = 0;
- }
-
- top.fetch_data = rom[top.addr];
- }
-
- trace.close();
- top.final(); // Done simulating
-}
diff --git a/tb/top/hps_sdram_test.cpp b/tb/top/hps_sdram_test.cpp
deleted file mode 100644
index b173c41..0000000
--- a/tb/top/hps_sdram_test.cpp
+++ /dev/null
@@ -1,93 +0,0 @@
-#include <cstdio>
-
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-
-#include "Vhps_sdram_test.h"
-#include "Vhps_sdram_test_hps_sdram_test.h"
-#include "Vhps_sdram_test_platform.h"
-
-#include "../avalon.hpp"
-#include "../mem.hpp"
-
-int main(int argc, char **argv)
-{
- using namespace taller::avalon;
-
- Verilated::commandArgs(argc, argv);
-
- Vhps_sdram_test top;
-
-#ifdef TRACE
- Verilated::traceEverOn(true);
- VerilatedVcdC trace;
-
- top.trace(&trace, 0);
- trace.open("trace.vcd");
-#endif
-
- interconnect<Vhps_sdram_test_platform> avl(*top.hps_sdram_test->plat);
- mem hps_ddr3(0x0000'0000, 512 << 20);
-
- avl.attach(hps_ddr3);
-
- int time = 0;
- top.clk_clk = 1;
-
- auto tick = [&]()
- {
- top.clk_clk = !top.clk_clk;
- top.eval();
- avl.tick(top.clk_clk);
-#ifdef TRACE
- trace.dump(time++);
-#endif
- };
-
- auto cycle = [&]()
- {
- tick();
- tick();
- std::printf("[%02d] out=0x%02x, done=%d\n", time, top.out, top.done);
- };
-
- auto io = [&]()
- {
- top.io = 0;
- cycle();
- top.io = 1;
- for(int i = 0; i < 4; ++i)
- {
- cycle();
- }
- };
-
- top.dir = 1;
- top.io = 1;
- top.mov = 1;
- top.clr = 1;
-
- for(int i = 0; i < 5; ++i)
- {
- top.add = 0;
- cycle();
- top.add = 1;
- cycle();
- }
-
- io();
-
- top.clr = 0;
- cycle();
- top.clr = 1;
- cycle();
-
- top.dir = 0;
- io();
-
-#ifdef TRACE
- trace.close();
-#endif
-
- top.final();
-}
diff --git a/tb/top/mul_test.cpp b/tb/top/mul_test.cpp
deleted file mode 100644
index cd99760..0000000
--- a/tb/top/mul_test.cpp
+++ /dev/null
@@ -1,71 +0,0 @@
-#include <cstdio>
-
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-
-#include "Vmul_test.h" // From Verilating "top.v"
-
-int main(int argc, char** argv) {
- Verilated::commandArgs(argc, argv); // Remember args
- Verilated::traceEverOn(true);
-
- Vmul_test top;
- VerilatedVcdC trace;
-
- top.trace(&trace, 0);
- trace.open("mul_test.vcd");
-
- top.a = 6;
- top.b = 5;
- top.clk = 0;
- top.rst = 0;
- top.start = 0;
- top.result = 0;
- top.rdy = 0;
- top.c_hi = 0;
- top.c_lo = 0;
-
-
- int clk_tick = 0;
- int time = 0;
-
- for(int i = 0; i < 100; ++i)
- {
- if(++clk_tick == 5)
- {
- clk_tick = 0;
- top.clk = !top.clk;
- }
-
-
- if(++clk_tick == 10)
- {
- top.rst = 1;
- }
-
- if(++clk_tick == 20)
- {
- top.start = 1;
- }
-
- if(++clk_tick == 30)
- {
- top.start = 0;
- }
-
- top.eval();
- trace.dump(time++);
-
- std::printf(" [%c%c%c%c]\n",
- top.n ? 'N' : 'n',
- top.z ? 'Z' : 'z',
- top.c ? 'C' : 'c',
- top.v ? 'V' : 'v');
-
- std::printf("a=%d, b=%d, ready=%d, result=%d, [N=%d, Z=%d]",
- top.a, top.b, top.rdy, top.result, top.n, top.z);
- }
-
- trace.close();
- top.final(); // Done simulating
-} \ No newline at end of file
diff --git a/tb/top/smp_sim.cpp b/tb/top/smp_sim.cpp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tb/top/smp_sim.cpp
diff --git a/tb/top/smp_sim.py b/tb/top/smp_sim.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tb/top/smp_sim.py
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 17:53:51 +0000