5 files changed, 91 insertions, 0 deletions
diff --git a/tb/models/__init__.py b/tb/models/__init__.py
new file mode 100644
index 0000000..4f14c05
--- /dev/null
+++ b/tb/models/__init__.py
@@ -0,0 +1,3 @@
+from .core import *
+from .smp import *
+
diff --git a/tb/models/core.py b/tb/models/core.py
new file mode 100644
index 0000000..c32fadb
--- /dev/null
+++ b/tb/models/core.py
@@ -0,0 +1,22 @@
+import random
+
+import cocotb
+from cocotb.triggers import ClockCycles
+
+class CorePaceModel:
+    def __init__(self, *, clk, halt, step, bkpt, halted):
+        self._clk = clk
+        self._halt = halt
+        self._step = step
+        self._bkpt = halted
+        self._halted = halted
+
+        self._bkpt.value = 0
+        self._halted.value = 0
+
+    async def run(self):
+        while True:
+            # Señales de step y halt pueden tomar algunas ciclos en surtir
+            # efecto, dependiendo de lo que esté ocurriendo en la pipeline
+            await ClockCycles(self._clk, random.randint(0, 10))
+            self._halted.value = self._step.value or self._halt.value
diff --git a/tb/models/smp.py b/tb/models/smp.py
new file mode 100644
index 0000000..a6439f8
--- /dev/null
+++ b/tb/models/smp.py
@@ -0,0 +1,22 @@
+__all__ = ['SmpModel']
+
+class SmpModel:
+    def __init__(self):
+        self._pe0 = SmpPe(0)
+        self._pe1 = SmpPe(1)
+        self._pe2 = SmpPe(1)
+        self._pe3 = SmpPe(1)
+
+    def read(self):
+        return self._pe0.read() \
+                | self._pe1.read() << 8 \
+                | self._pe2.read() << 16 \
+                | self._pe3.read() << 24
+
+class SmpPe:
+    def __init__(self, halt_on_reset):
+        self._bkpt = 0
+        self._halted = halt_on_reset
+
+    def read(self):
+        return self._bkpt << 1 | self._halted
diff --git a/tb/top/smp_sim.cpp b/tb/top/smp_sim.cpp
index e69de29..4b58019 100644
--- a/tb/top/smp_sim.cpp
+++ b/tb/top/smp_sim.cpp
@@ -0,0 +1 @@
+// No necesitamos nada aquí, todo lo genera verilator+cocotb
diff --git a/tb/top/smp_sim.py b/tb/top/smp_sim.py
index e69de29..1994da2 100644
--- a/tb/top/smp_sim.py
+++ b/tb/top/smp_sim.py
@@ -0,0 +1,43 @@
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import Combine, ClockCycles, RisingEdge, Timer, with_timeout
+from cocotb_bus.drivers.avalon import AvalonMaster
+
+from tb.models import CorePaceModel, SmpModel
+
+@cocotb.test()
+async def reset(dut):
+    dut.rst_n.value = 1
+    await Timer(1)
+    dut.rst_n.value = 0
+    await Timer(1)
+    dut.rst_n.value = 1
+
+    model = SmpModel()
+
+    cocotb.start_soon(Clock(dut.clk, 2).start())
+    master = AvalonMaster(dut, 'avl', dut.clk, case_insensitive=False)
+
+    cpu0 = CorePaceModel(clk=dut.clk, halt=dut.halt_0, step=dut.step_0,
+                         bkpt=dut.breakpoint_0, halted=dut.cpu_halted_0)
+
+    cpu1 = CorePaceModel(clk=dut.clk, halt=dut.halt_1, step=dut.step_1,
+                         bkpt=dut.breakpoint_1, halted=dut.cpu_halted_1)
+
+    cpu2 = CorePaceModel(clk=dut.clk, halt=dut.halt_2, step=dut.step_2,
+                         bkpt=dut.breakpoint_2, halted=dut.cpu_halted_2)
+
+    cpu3 = CorePaceModel(clk=dut.clk, halt=dut.halt_3, step=dut.step_3,
+                         bkpt=dut.breakpoint_3, halted=dut.cpu_halted_3)
+
+    cocotb.start_soon(cpu0.run())
+    cocotb.start_soon(cpu1.run())
+    cocotb.start_soon(cpu2.run())
+    cocotb.start_soon(cpu3.run())
+
+    await with_timeout(Combine(*(RisingEdge(halted) for halted in
+                                 [dut.cpu_halted_1, dut.cpu_halted_2, dut.cpu_halted_3])),
+                       50)
+
+    await ClockCycles(dut.clk, 5)
+    assert await master.read(0) == model.read()