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-rw-r--r--tb/avalon.hpp3
-rw-r--r--tb/avalon.impl.hpp3
-rw-r--r--tb/platform.sv23
-rw-r--r--tb/sim_slave.cpp60
-rw-r--r--tb/sim_slave.hpp36
-rw-r--r--tb/sim_slave.sv28
-rw-r--r--tb/top/conspiracion.cpp17
7 files changed, 157 insertions, 13 deletions
diff --git a/tb/avalon.hpp b/tb/avalon.hpp
index 6c720bc..b184999 100644
--- a/tb/avalon.hpp
+++ b/tb/avalon.hpp
@@ -98,6 +98,9 @@ namespace taller::avalon
inline virtual void tick() noexcept
{}
+ inline virtual void tick_falling() noexcept
+ {}
+
inline virtual void bail() noexcept
{}
diff --git a/tb/avalon.impl.hpp b/tb/avalon.impl.hpp
index efae0b9..12483f9 100644
--- a/tb/avalon.impl.hpp
+++ b/tb/avalon.impl.hpp
@@ -120,6 +120,9 @@ namespace taller::avalon
template<class Platform>
void interconnect<Platform>::tick_falling() noexcept
{
+ for (auto &binding : devices)
+ binding.dev.tick_falling();
+
if (!plat.avl_waitrequest)
active = nullptr;
}
diff --git a/tb/platform.sv b/tb/platform.sv
index 13b94d7..fddf6e8 100644
--- a/tb/platform.sv
+++ b/tb/platform.sv
@@ -310,6 +310,21 @@ module platform
.*
);
+ word smp_readdata, smp_writedata;
+ logic smp_read, smp_write;
+
+ sim_slave smp_sim
+ (
+ .read(smp_read),
+ .write(smp_write),
+ .address(),
+ .readdata(smp_readdata),
+ .writedata(smp_writedata),
+ .waitrequest(0),
+
+ .*
+ );
+
logic step_0, step_1, step_2, step_3,
halt_0, halt_1, halt_2, halt_3,
breakpoint_0, breakpoint_1, breakpoint_2, breakpoint_3,
@@ -317,10 +332,10 @@ module platform
smp_ctrl smp
(
- .avl_read(0),
- .avl_write(0),
- .avl_writedata(),
- .avl_readdata(),
+ .avl_read(smp_read),
+ .avl_write(smp_write),
+ .avl_writedata(smp_writedata),
+ .avl_readdata(smp_readdata),
.*
);
diff --git a/tb/sim_slave.cpp b/tb/sim_slave.cpp
new file mode 100644
index 0000000..24528d2
--- /dev/null
+++ b/tb/sim_slave.cpp
@@ -0,0 +1,60 @@
+#include <cstdint>
+
+#include "avalon.hpp"
+#include "sim_slave.hpp"
+
+namespace taller::avalon
+{
+ sim_slave::sim_slave(verilated_slave &dev, std::uint32_t base, std::uint32_t size)
+ : slave(base, size, 4),
+ dev(dev)
+ {
+ dev.avl_read = 0;
+ dev.avl_write = 0;
+ }
+
+ void sim_slave::tick() noexcept
+ {
+ if (latch) {
+ dev.avl_read = 0;
+ dev.avl_write = 0;
+ }
+ }
+
+ void sim_slave::tick_falling() noexcept
+ {
+ if ((dev.avl_read || dev.avl_write) && !dev.avl_waitrequest) {
+ latch = true;
+ latch_readdata = dev.avl_readdata;
+ }
+ }
+
+ bool sim_slave::read(std::uint32_t addr, std::uint32_t &data)
+ {
+ if (latch) {
+ data = latch_readdata;
+
+ latch = false;
+ return true;
+ } else if (!dev.avl_read && !dev.avl_write) {
+ dev.avl_read = 1;
+ dev.avl_address = addr;
+ }
+
+ return false;
+ }
+
+ bool sim_slave::write(std::uint32_t addr, std::uint32_t data, unsigned byte_enable)
+ {
+ if (latch) {
+ latch = false;
+ return true;
+ } else if (!dev.avl_read && !dev.avl_write) {
+ dev.avl_write = 1;
+ dev.avl_address = addr;
+ dev.avl_writedata = data;
+ }
+
+ return false;
+ }
+}
diff --git a/tb/sim_slave.hpp b/tb/sim_slave.hpp
new file mode 100644
index 0000000..cdcea78
--- /dev/null
+++ b/tb/sim_slave.hpp
@@ -0,0 +1,36 @@
+#ifndef TALLER_SIM_SLAVE_HPP
+#define TALLER_SIM_SLAVE_HPP
+
+#include <cstdint>
+
+#include "Vconspiracion_sim_slave.h"
+
+#include "avalon.hpp"
+
+namespace taller::avalon
+{
+ using verilated_slave = Vconspiracion_sim_slave;
+
+ class sim_slave : public slave
+ {
+ public:
+ sim_slave(verilated_slave &dev, std::uint32_t base, std::uint32_t size);
+
+ virtual void tick() noexcept final override;
+ virtual void tick_falling() noexcept final override;
+
+ virtual bool read(std::uint32_t addr, std::uint32_t &data) final override;
+
+ virtual bool write
+ (
+ std::uint32_t addr, std::uint32_t data, unsigned byte_enable = 0b1111
+ ) final override;
+
+ private:
+ verilated_slave &dev;
+ bool latch;
+ std::uint32_t latch_readdata;
+ };
+}
+
+#endif
diff --git a/tb/sim_slave.sv b/tb/sim_slave.sv
new file mode 100644
index 0000000..1598701
--- /dev/null
+++ b/tb/sim_slave.sv
@@ -0,0 +1,28 @@
+module sim_slave
+(
+ input logic clk,
+
+ input logic waitrequest,
+ input logic[31:0] readdata,
+ output logic[31:0] address,
+ writedata,
+ output logic read,
+ write
+);
+
+ logic[31:0] avl_address /*verilator public_flat_rw @(negedge clk)*/;
+ logic avl_read /*verilator public_flat_rw @(negedge clk)*/;
+ logic avl_write /*verilator public_flat_rw @(negedge clk)*/;
+ logic[31:0] avl_readdata /*verilator public*/;
+ logic[31:0] avl_writedata /*verilator public_flat_rw @(negedge clk)*/;
+ logic avl_waitrequest /*verilator public*/;
+
+ assign read = avl_read;
+ assign write = avl_write;
+ assign address = avl_address;
+ assign writedata = avl_writedata;
+
+ assign avl_readdata = readdata;
+ assign avl_waitrequest = waitrequest;
+
+endmodule
diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp
index e28fcfc..a740240 100644
--- a/tb/top/conspiracion.cpp
+++ b/tb/top/conspiracion.cpp
@@ -17,6 +17,7 @@
#include "Vconspiracion_arm810.h"
#include "Vconspiracion_conspiracion.h"
#include "Vconspiracion_platform.h"
+#include "Vconspiracion_sim_slave.h"
#include "Vconspiracion_vga_domain.h"
#include "Vconspiracion_core.h"
#include "Vconspiracion_core_control.h"
@@ -44,6 +45,7 @@
#include "../jtag_uart.hpp"
#include "../interval_timer.hpp"
#include "../null.hpp"
+#include "../sim_slave.hpp"
#include "../window.hpp"
#include "../vga.hpp"
@@ -331,6 +333,8 @@ int main(int argc, char **argv)
*plat.vga, 0x3800'0000, 25'175'000, 50'000'000
);
+ sim_slave smp_ctrl(*plat.smp_sim, 0x3014'0000, 4);
+
interconnect<Vconspiracion_platform> avl(plat);
//interconnect<Vconspiracion_vga_domain> avl_vga(plat->vga);
@@ -346,24 +350,19 @@ int main(int argc, char **argv)
avl.attach(hps_ddr3);
avl.attach(timer);
avl.attach(ttyJ0);
+ avl.attach(smp_ctrl);
avl.attach_intc(intc);
- for(auto &slave : consts)
- {
+ for (auto &slave : consts)
avl.attach(slave);
- }
- if(enable_fast_video)
- {
+ if (enable_fast_video)
avl.attach(vga);
- } else if(enable_accurate_video)
- {
+ else if(enable_accurate_video) {
avl.attach(vram);
//avl_vga.attach(vram_window);
} else
- {
avl.attach(vram_null);
- }
FILE *img_file = std::fopen(image->c_str(), "rb");
if(!img_file)
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 16:32:38 +0000