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-rw-r--r--tb/top/decode_test.cpp50
-rw-r--r--tb/top/mul_test.cpp32
2 files changed, 51 insertions, 31 deletions
diff --git a/tb/top/decode_test.cpp b/tb/top/decode_test.cpp
new file mode 100644
index 0000000..3d8589a
--- /dev/null
+++ b/tb/top/decode_test.cpp
@@ -0,0 +1,50 @@
+#include <cstdio>
+
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+
+#include "Vdecode_test.h" // From Verilating "top.v"
+
+int main(int argc, char** argv) {
+ Verilated::commandArgs(argc, argv); // Remember args
+ Verilated::traceEverOn(true);
+
+ Vdecode_test top;
+ VerilatedVcdC trace;
+
+ top.trace(&trace, 0);
+ trace.open("decode_test.vcd");
+
+ int instructions[4] = {};
+ top.n = 0;
+ top.z = 0;
+ top.c = 0;
+ top.v = 0;
+
+ int clk_tick = 0;
+ int time = 0;
+
+ for(int i = 0; i < sizeof(instructions); ++i)
+ {
+ top.insn = instructions[i];
+ top.n = 0;
+ top.z = 0;
+ top.c = 0;
+ top.v = 0;
+
+ top.eval();
+ trace.dump(time++);
+
+ std::printf(" [%c%c%c%c]\n",
+ top.n ? 'N' : 'n',
+ top.z ? 'Z' : 'z',
+ top.c ? 'C' : 'c',
+ top.v ? 'V' : 'v');
+
+ std::printf("insn=%d, ctrl=%d",
+ instructions[i], top.ctrl);
+ }
+
+ trace.close();
+ top.final(); // Done simulating
+}
diff --git a/tb/top/mul_test.cpp b/tb/top/mul_test.cpp
index 1dcebdc..cd99760 100644
--- a/tb/top/mul_test.cpp
+++ b/tb/top/mul_test.cpp
@@ -68,34 +68,4 @@ int main(int argc, char** argv) {
trace.close();
top.final(); // Done simulating
-}
-
-/*
-
-module mul_tb();
-
- logic clk,rst,start;
- logic[7:0]X,Y;
- logic[15:0]Z;
- logic valid;
-
- always #5 clk = ~clk;
-
- core_mul_mul #(.W(8)) inst (.clk(clk),.rst(rst),.start(start),.a(X),.b(Y),.rdy(valid),.result(Z));
-
- initial
- $monitor($time,"a=%d, b=%d, ready=%d, Z=%d ",X,Y,valid,Z);
- initial
- begin
- X=255;Y=150;clk=1'b1;rst=1'b0;start=1'b0;
- #10 rst = 1'b1;
- #10 start = 1'b1;
- #10 start = 1'b0;
- @valid
- #10 X=-80;Y=-10;start = 1'b1;
- #10 start = 1'b0;
- end
-endmodule
-
-
-*/ \ No newline at end of file
+} \ No newline at end of file