7 files changed, 122 insertions, 0 deletions
diff --git a/tb/sim/shifts.S b/tb/sim/shifts.S
new file mode 100644
index 0000000..68ef3f8
--- /dev/null
+++ b/tb/sim/shifts.S
@@ -0,0 +1,17 @@
+.global reset
+reset:
+	ldr r0, =0xffffffff
+	ldr r1, =0xbaaaaa9f
+	ldr r2, =0x00000054
+	ldr r3, =0xfffffffe
+	# r3 = 5d55
+	lsr r3, r1, #17
+	# r0 = 15000
+	lsl r0, r2, #10
+	# tmp = aaa9f000
+	# r3 = aaa9fd55
+	orr r3, r3, r1, lsl #12
+	# tmp = 0
+	# r2 = r0 = 00015000
+	eor r2, r0, r2, asr #7
+	mov pc, lr
diff --git a/tb/sim/shifts.py b/tb/sim/shifts.py
new file mode 100644
index 0000000..38f24a2
--- /dev/null
+++ b/tb/sim/shifts.py
@@ -0,0 +1,4 @@
+def final():
+	assert_reg(r0, 0x00015000)
+	assert_reg(r2, 0x00015000)
+	assert_reg(r3, 0xaaa9fd55)
diff --git a/tb/sim/sim.py b/tb/sim/sim.py
index f94d259..5d3ecd5 100755
--- a/tb/sim/sim.py
+++ b/tb/sim/sim.py
@@ -264,4 +264,10 @@ for line in output.stdout.split('\n'):
 if final := module_get('final'):
     final()
 
+if os.getenv('SIM_DUMP', ''):
+    dump_regs()
+    for rng in mem_dumps:
+        print(f'Memory range 0x{rng.start:08x}..0x{rng.stop:08x}')
+        print(hexdump(rng.start, read_mem(rng.start, rng.stop - rng.start)))
+
 exit(success=True)
diff --git a/tb/sim/stack.S b/tb/sim/stack.S
new file mode 100644
index 0000000..f1bc0a8
--- /dev/null
+++ b/tb/sim/stack.S
@@ -0,0 +1,20 @@
+.global reset
+reset:
+	ldr  r0, =stub1
+	ldr  r1, =stub2
+	push {r0, r1, lr}
+	mov  r2, sp
+	pop  {r5, pc}
+
+stub1:
+	ldr  r0, =0x01234567
+	pop  {pc}
+
+stub2:
+	mov  r3, sp
+	ldr  r1, =0x89abcdef
+	push {r5}
+	mov  r4, sp
+	pop  {lr}
+	mov  r5, sp
+	mov  pc, lr
diff --git a/tb/sim/stack.py b/tb/sim/stack.py
new file mode 100644
index 0000000..c1f4e7f
--- /dev/null
+++ b/tb/sim/stack.py
@@ -0,0 +1,8 @@
+def final():
+    assert_reg(r0, 0x0123_4567)
+    assert_reg(r1, 0x89ab_cdef)
+    assert_reg(r2, 0x1fff_fff4)
+    assert_reg(r3, 0x1fff_fffc)
+    assert_reg(r4, 0x1fff_fff8)
+    assert_reg(r5, 0x1fff_fffc)
+    assert_reg(sp_svc, 0x2000_0000)
diff --git a/tb/sim/tarea2.S b/tb/sim/tarea2.S
new file mode 100644
index 0000000..c372672
--- /dev/null
+++ b/tb/sim/tarea2.S
@@ -0,0 +1,44 @@
+@ Tarea 2, CE3201 Taller de Diseño Digital
+@ Alejandro Soto Chacón, 2019008164
+
+.global fibonacci
+fibonacci:
+	mov   r0, #0x150
+	ldr   r0, [r0]
+	mov   r1, #0x200
+	mov   r2, #1
+	mov   r3, #1
+	mov   r4, #0
+	tst   r0, r0
+	beq   .end
+	ldr   r6, =10000 @ Relativo a PC
+	.loop:
+	add   r5, r2, r3
+	add   r4, r4, r2
+	str   r2, [r1], #4
+	mov   r2, r3
+	mov   r3, r5
+	cmp   r4, r6
+	bhi   .end
+	subs  r0, r0, #1
+	bne   .loop
+	.end:
+	mov   r5, #0x100
+	str   r4, [r5], #4
+	mov   r4, #0xff
+	mov   r6, #0xaa
+	@ Necesariamente se cumple alguna de las dos condiciones
+	@ ya que una es la opuesta de la otra
+	strhi r4, [r5]
+	strls r6, [r5]
+	mov   pc, lr
+
+@ Punto de entrada, requerido ya que el simulador solamente es capaz
+@ ed establecer condiciones iniciales de registros, no de memoria.
+@ En este caso se pasa el número de iteraciones en r0 y el stub lo
+@ escribe en la posición correcta.
+.global reset
+reset:
+	mov r1, #0x150
+	str r0, [r1]
+	b   fibonacci
diff --git a/tb/sim/tarea2.py b/tb/sim/tarea2.py
new file mode 100644
index 0000000..921ea6f
--- /dev/null
+++ b/tb/sim/tarea2.py
@@ -0,0 +1,23 @@
+N = 20
+
+mem_dumps = [range(0x100, 0x108), range(0x200, 0x200 + 4 * N)]
+
+def init():
+    init_reg(r0, N)
+
+def final():
+    a, b, s = 1, 1, 0
+    mem = []
+
+    for _ in range(N):
+        s += a
+        c = a + b
+        mem.append(a)
+        a, b = b, c
+
+        if s > 10000:
+            break
+
+    assert_reg(r5, 0x104)
+    assert_mem(0x100, [s, 0xff if s > 10000 else 0xaa])
+    assert_mem(0x200, mem)