9 files changed, 185 insertions, 92 deletions
diff --git a/tb/sim/descifrador.S b/tb/sim/descifrador.S
deleted file mode 100644
index 84b529c..0000000
--- a/tb/sim/descifrador.S
+++ /dev/null
@@ -1,72 +0,0 @@
-.global reset
-reset:
-
-@ IO utilizado:
-@  5 switches para la llave
-@  1 switch de selección de algoritmo (xor o not)
-@  1 botón de inicio
-
-.equ START_BUTTON, 0x30050000 @ Dirección de memoria del botón
-.equ KEY_SWITCHES, 0x30060000 @ Dirección de memoria de los switches
-.equ START, 0x00010000 @ Dirección de memoria de los pixeles
-.equ VRAM, 0x38000000 
-
-@ Dirección inicial de lectura, contador y tamaño de la imagen
-ldr r1, =START
-ldr r11, =VRAM
-mov r7, #0x0
-ldr r8, =(640*480)
-
-init:
-  ldr  r4, [r1], #4 	@ Guarda en r4 el dato en la posición de memoria de start
-  str  r4, [r11], #4  @ Vuelve a guardar en memoria ya modificado
-  add  r7, r7, #1  	  @ Incrementa contador de tamaño de la imagen
-  cmp  r7, r8    	@ Compara contador con tamaño de la imagen 640 * 480
-  bne  init
-
-ldr r1, =START
-ldr r11, =VRAM
-mov r7, #0x0
-
-@Esperar botón
-ldr r2, =START_BUTTON
-ldr r3, =KEY_SWITCHES
-
-idle:
-  ldr r5, [r2]  @ Lee valor del botón
-  ldr r6, [r3]  @ Lee valores de los switches 
-  tst r5, #1    @ Si el botón de inicio es 1, se salta a start
-  beq idle
-
-@ Verificar el algoritmo seleccionado
-tst r6, #1    	@ Si el valor es 1, se salta a xor, si es 0 a not
-bne xor
-  
-@ Recorrer la memoria desde START y hacer not al valor en cada posicion
-@ y volverlo a guardar
-not:
-  @Procesar la mask
-  ldr r0, =0x00ffffff
-	b loop
-
-xor:
-@Procesar la llave
-	lsr r9, r6, #1
-	mov r0, r9
-	orr r0, r0, r9, lsl #8
-	orr r0, r0, r9, lsl #16
-
-loop:
-  ldr  r4, [r1] 	@ Guarda en r4 el dato en la posición de memoria de start
-  eor  r4, r4, r0  	  @ Hace XOR entre r4 
-  str  r4, [r1], #4  @ Vuelve a guardar en memoria ya modificado
-  add  r7, r7, #1  	  @ Incrementa contador de tamaño de la imagen
-  cmp  r7, r8    	@ Compara contador con tamaño de la imagen 640 * 480
-  bne  loop
-
-release:
-  ldr r5, [r2]  @ Lee valor del botón
-  tst r5, #1    @ Si el botón de inicio es 1, se salta a start
-  bne release
-
-  b reset
-\ No newline at end of file
diff --git a/tb/sim/descifrador.py b/tb/sim/descifrador.py
deleted file mode 100644
index a77375b..0000000
--- a/tb/sim/descifrador.py
+++ /dev/null
@@ -1,20 +0,0 @@
-LOG = 'image_processing/log'
-FILE = 'image_processing/out_file'
-SIZE = 640 * 480 * 4
-START = 0x10000
-
-loads = {START: FILE}
-consts = {0x30050000: 1, 0x30060000: 0}
-cycles = 23000000
-mem_dumps = [range(START, START + SIZE)]
-enable_video = True
-
-def final():
-    words = []
-    with open(FILE, 'rb') as file:
-        while data := file.read(4):
-            words.append(int.from_bytes(data, 'little') ^ 0x00ffffff)
-
-    assert_mem(START, words)
-    with open(LOG, 'w') as log:
-        print(read_mem(START, SIZE), file=log)
diff --git a/tb/sim/smp_boot.S b/tb/sim/smp_boot.S
new file mode 100644
index 0000000..669508b
--- /dev/null
+++ b/tb/sim/smp_boot.S
@@ -0,0 +1,25 @@
+.global reset
+
+reset:
+	adr   r0, cpus
+
+.inc_cpus:
+	ldrex r1, [r0]
+	add   r1, r1, #1
+	strex r2, r1, [r0]
+	teq   r2, #0
+	bne   .inc_cpus
+
+	cmp   r1, #1
+	movne pc, lr
+
+	ldr   r1, =0x30140000
+	ldr   r2, [r1]
+	ldr   r3, =0x01010100
+	str   r3, [r1]
+	ldr   r3, [r1]
+.wait:
+	ldr   r1, [r0]
+	b     .wait
+
+cpus: .word 0
diff --git a/tb/sim/smp_boot.py b/tb/sim/smp_boot.py
new file mode 100644
index 0000000..40c3012
--- /dev/null
+++ b/tb/sim/smp_boot.py
@@ -0,0 +1,4 @@
+def final():
+    assert_reg(r1, 4)
+    assert_reg(r2, 0x01010100)
+    assert_reg(r3, 0)
diff --git a/tb/sim/strex.S b/tb/sim/strex.S
new file mode 100644
index 0000000..575a839
--- /dev/null
+++ b/tb/sim/strex.S
@@ -0,0 +1,23 @@
+.global reset
+
+reset:
+	ldr   r0, =0x1000
+	ldr   r1, =0x01234567
+	str   r1, [r0]
+	mvn   r1, r1
+	str   r1, [r0, #4]
+	mov   r12, lr
+	swi   #0
+	mov   lr, r12
+	strex r2, r0, [r0] @ Debe fallar
+	ldrex r3, [r0]
+	add   r0, r0, #4
+	ldrex r4, [r0]
+	strex r5, r3, [r0] @ Debe fallar
+	sub   r0, r0, #4
+	strex r6, r4, [r0] @ Debe servir
+	mov   pc, lr
+
+.global swi
+swi:
+	movs  pc, lr
diff --git a/tb/sim/strex.py b/tb/sim/strex.py
new file mode 100644
index 0000000..d53c355
--- /dev/null
+++ b/tb/sim/strex.py
@@ -0,0 +1,9 @@
+mem_dumps = [range(0x1000, 0x1008)]
+
+def final():
+    assert_reg(r2, 1)
+    assert_reg(r5, 1)
+    assert_reg(r6, 0)
+
+    assert_mem(0x1000, 0xfedcba98)
+    assert_mem(0x1004, 0x01234567)
diff --git a/tb/sim_slave.cpp b/tb/sim_slave.cpp
new file mode 100644
index 0000000..24528d2
--- /dev/null
+++ b/tb/sim_slave.cpp
@@ -0,0 +1,60 @@
+#include <cstdint>
+
+#include "avalon.hpp"
+#include "sim_slave.hpp"
+
+namespace taller::avalon
+{
+	sim_slave::sim_slave(verilated_slave &dev, std::uint32_t base, std::uint32_t size)
+	: slave(base, size, 4),
+	  dev(dev)
+	{
+		dev.avl_read = 0;
+		dev.avl_write = 0;
+	}
+
+	void sim_slave::tick() noexcept
+	{
+		if (latch) {
+			dev.avl_read = 0;
+			dev.avl_write = 0;
+		}
+	}
+
+	void sim_slave::tick_falling() noexcept
+	{
+		if ((dev.avl_read || dev.avl_write) && !dev.avl_waitrequest) {
+			latch = true;
+			latch_readdata = dev.avl_readdata;
+		}
+	}
+
+	bool sim_slave::read(std::uint32_t addr, std::uint32_t &data)
+	{
+		if (latch) {
+			data = latch_readdata;
+
+			latch = false;
+			return true;
+		} else if (!dev.avl_read && !dev.avl_write) {
+			dev.avl_read = 1;
+			dev.avl_address = addr;
+		}
+
+		return false;
+	}
+
+	bool sim_slave::write(std::uint32_t addr, std::uint32_t data, unsigned byte_enable)
+	{
+		if (latch) {
+			latch = false;
+			return true;
+		} else if (!dev.avl_read && !dev.avl_write) {
+			dev.avl_write = 1;
+			dev.avl_address = addr;
+			dev.avl_writedata = data;
+		}
+
+		return false;
+	}
+}
diff --git a/tb/sim_slave.hpp b/tb/sim_slave.hpp
new file mode 100644
index 0000000..cdcea78
--- /dev/null
+++ b/tb/sim_slave.hpp
@@ -0,0 +1,36 @@
+#ifndef TALLER_SIM_SLAVE_HPP
+#define TALLER_SIM_SLAVE_HPP
+
+#include <cstdint>
+
+#include "Vconspiracion_sim_slave.h"
+
+#include "avalon.hpp"
+
+namespace taller::avalon
+{
+	using verilated_slave = Vconspiracion_sim_slave;
+
+	class sim_slave : public slave
+	{
+		public:
+			sim_slave(verilated_slave &dev, std::uint32_t base, std::uint32_t size);
+
+			virtual void tick() noexcept final override;
+			virtual void tick_falling() noexcept final override;
+
+			virtual bool read(std::uint32_t addr, std::uint32_t &data) final override;
+
+			virtual bool write
+			(
+				std::uint32_t addr, std::uint32_t data, unsigned byte_enable = 0b1111
+			) final override;
+
+		private:
+			verilated_slave &dev;
+			bool             latch;
+			std::uint32_t    latch_readdata;
+	};
+}
+
+#endif
diff --git a/tb/sim_slave.sv b/tb/sim_slave.sv
new file mode 100644
index 0000000..1598701
--- /dev/null
+++ b/tb/sim_slave.sv
@@ -0,0 +1,28 @@
+module sim_slave
+(
+	input  logic       clk,
+
+	input  logic       waitrequest,
+	input  logic[31:0] readdata,
+	output logic[31:0] address,
+	                   writedata,
+	output logic       read,
+	                   write
+);
+
+	logic[31:0] avl_address /*verilator public_flat_rw @(negedge clk)*/;
+	logic       avl_read /*verilator public_flat_rw @(negedge clk)*/;
+	logic       avl_write /*verilator public_flat_rw @(negedge clk)*/;
+	logic[31:0] avl_readdata /*verilator public*/;
+	logic[31:0] avl_writedata /*verilator public_flat_rw @(negedge clk)*/;
+	logic       avl_waitrequest /*verilator public*/;
+
+	assign read = avl_read;
+	assign write = avl_write;
+	assign address = avl_address;
+	assign writedata = avl_writedata;
+
+	assign avl_readdata = readdata;
+	assign avl_waitrequest = waitrequest;
+
+endmodule