3 files changed, 124 insertions, 0 deletions
diff --git a/tb/sim_slave.cpp b/tb/sim_slave.cpp
new file mode 100644
index 0000000..24528d2
--- /dev/null
+++ b/tb/sim_slave.cpp
@@ -0,0 +1,60 @@
+#include <cstdint>
+
+#include "avalon.hpp"
+#include "sim_slave.hpp"
+
+namespace taller::avalon
+{
+	sim_slave::sim_slave(verilated_slave &dev, std::uint32_t base, std::uint32_t size)
+	: slave(base, size, 4),
+	  dev(dev)
+	{
+		dev.avl_read = 0;
+		dev.avl_write = 0;
+	}
+
+	void sim_slave::tick() noexcept
+	{
+		if (latch) {
+			dev.avl_read = 0;
+			dev.avl_write = 0;
+		}
+	}
+
+	void sim_slave::tick_falling() noexcept
+	{
+		if ((dev.avl_read || dev.avl_write) && !dev.avl_waitrequest) {
+			latch = true;
+			latch_readdata = dev.avl_readdata;
+		}
+	}
+
+	bool sim_slave::read(std::uint32_t addr, std::uint32_t &data)
+	{
+		if (latch) {
+			data = latch_readdata;
+
+			latch = false;
+			return true;
+		} else if (!dev.avl_read && !dev.avl_write) {
+			dev.avl_read = 1;
+			dev.avl_address = addr;
+		}
+
+		return false;
+	}
+
+	bool sim_slave::write(std::uint32_t addr, std::uint32_t data, unsigned byte_enable)
+	{
+		if (latch) {
+			latch = false;
+			return true;
+		} else if (!dev.avl_read && !dev.avl_write) {
+			dev.avl_write = 1;
+			dev.avl_address = addr;
+			dev.avl_writedata = data;
+		}
+
+		return false;
+	}
+}
diff --git a/tb/sim_slave.hpp b/tb/sim_slave.hpp
new file mode 100644
index 0000000..cdcea78
--- /dev/null
+++ b/tb/sim_slave.hpp
@@ -0,0 +1,36 @@
+#ifndef TALLER_SIM_SLAVE_HPP
+#define TALLER_SIM_SLAVE_HPP
+
+#include <cstdint>
+
+#include "Vconspiracion_sim_slave.h"
+
+#include "avalon.hpp"
+
+namespace taller::avalon
+{
+	using verilated_slave = Vconspiracion_sim_slave;
+
+	class sim_slave : public slave
+	{
+		public:
+			sim_slave(verilated_slave &dev, std::uint32_t base, std::uint32_t size);
+
+			virtual void tick() noexcept final override;
+			virtual void tick_falling() noexcept final override;
+
+			virtual bool read(std::uint32_t addr, std::uint32_t &data) final override;
+
+			virtual bool write
+			(
+				std::uint32_t addr, std::uint32_t data, unsigned byte_enable = 0b1111
+			) final override;
+
+		private:
+			verilated_slave &dev;
+			bool             latch;
+			std::uint32_t    latch_readdata;
+	};
+}
+
+#endif
diff --git a/tb/sim_slave.sv b/tb/sim_slave.sv
new file mode 100644
index 0000000..1598701
--- /dev/null
+++ b/tb/sim_slave.sv
@@ -0,0 +1,28 @@
+module sim_slave
+(
+	input  logic       clk,
+
+	input  logic       waitrequest,
+	input  logic[31:0] readdata,
+	output logic[31:0] address,
+	                   writedata,
+	output logic       read,
+	                   write
+);
+
+	logic[31:0] avl_address /*verilator public_flat_rw @(negedge clk)*/;
+	logic       avl_read /*verilator public_flat_rw @(negedge clk)*/;
+	logic       avl_write /*verilator public_flat_rw @(negedge clk)*/;
+	logic[31:0] avl_readdata /*verilator public*/;
+	logic[31:0] avl_writedata /*verilator public_flat_rw @(negedge clk)*/;
+	logic       avl_waitrequest /*verilator public*/;
+
+	assign read = avl_read;
+	assign write = avl_write;
+	assign address = avl_address;
+	assign writedata = avl_writedata;
+
+	assign avl_readdata = readdata;
+	assign avl_waitrequest = waitrequest;
+
+endmodule