diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/core/control/control.sv | 19 | ||||
| -rw-r--r-- | rtl/core/control/select.sv | 48 |
2 files changed, 55 insertions, 12 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index cc8f160..629e1d9 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -56,7 +56,7 @@ module core_control logic ldst, ldst_pre, ldst_increment, ldst_writeback, pop_valid; word mem_offset; - reg_num r_shift, popped_upper, popped_lower, popped; + reg_num popped_upper, popped_lower, popped; reg_list mem_regs, next_regs_upper, next_regs_lower; assign reg_mode = `MODE_SVC; //TODO @@ -85,6 +85,11 @@ module core_control .* ); + core_control_select ctrl_select + ( + .* + ); + core_control_ldst_pop ctrl_ldst_pop ( .regs(mem_regs), @@ -130,10 +135,6 @@ module core_control unique case(next_cycle) ISSUE: if(issue) begin - ra <= dec_data.rn; - rb <= dec_snd.r; - r_shift <= dec_snd.r_shift; - // TODO: dec_ldst.unprivileged/user_regs // TODO: byte/halfword sizes ldst <= dec.ldst; @@ -152,8 +153,7 @@ module core_control mem_write <= !dec_ldst.load; end - RD_INDIRECT_SHIFT: - rb <= r_shift; + RD_INDIRECT_SHIFT: ; WITH_SHIFT: ; @@ -166,11 +166,6 @@ module core_control if(cycle != TRANSFER || mem_ready) begin mem_regs <= ldst_increment ? next_regs_lower : next_regs_upper; mem_addr <= ldst_pre ? q_alu[31:2] : alu_a[31:2]; - - if(pop_valid) - rb <= popped; - else - rb <= final_rd; // Viene de dec_ldst.rd end mem_start <= cycle != TRANSFER || (mem_ready && pop_valid); diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv new file mode 100644 index 0000000..a073e24 --- /dev/null +++ b/rtl/core/control/select.sv @@ -0,0 +1,48 @@ +`include "core/uarch.sv" + +module core_control_select +( + input logic clk, + + input data_decode dec_data, + input snd_decode dec_snd, + + input ctrl_cycle cycle, + next_cycle, + input logic issue, + mem_ready, + pop_valid, + input reg_num popped, + final_rd, + + output reg_num ra, + rb +); + + reg_num r_shift; + + always_ff @(posedge clk) + unique0 case(next_cycle) + ISSUE: + if(issue) begin + ra <= dec_data.rn; + rb <= dec_snd.r; + r_shift <= dec_snd.r_shift; + end + + RD_INDIRECT_SHIFT: + rb <= r_shift; + + TRANSFER: + if(cycle != TRANSFER || mem_ready) + // final_rd viene de dec_ldst.rd + rb <= pop_valid ? popped : final_rd; + endcase + + initial begin + ra = {$bits(ra){1'b0}}; + rb = {$bits(rb){1'b0}}; + r_shift = {$bits(r_shift){1'b0}}; + end + +endmodule |