diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/bus/master.sv | 4 | ||||
| -rw-r--r-- | rtl/top/conspiracion.sv | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv index d350d80..6e29ac2 100644 --- a/rtl/bus/master.sv +++ b/rtl/bus/master.sv @@ -8,7 +8,7 @@ module bus_master write, output logic ready, output logic[31:0] data_rd, - input logic[31:0] data_rw, + input logic[31:0] data_wr, output logic[31:0] avl_address, output logic avl_read, @@ -33,7 +33,7 @@ module bus_master avl_address <= {addr, 2'b00}; avl_read <= ~write; avl_write <= write; - avl_writedata <= data_rw; + avl_writedata <= data_wr; state <= WAIT; end diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 174dceb..30aa95f 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -31,7 +31,7 @@ module conspiracion } state; logic[29:0] addr; - logic[31:0] data_rd, data_rw; + logic[31:0] data_rd, data_wr; logic ready, write, start; logic [7:0] leds; @@ -40,7 +40,7 @@ module conspiracion ( .master_0_core_addr(addr), .master_0_core_data_rd(data_rd), - .master_0_core_data_rw(data_rw), + .master_0_core_data_wr(data_wr), .master_0_core_ready(ready), .master_0_core_write(write), .master_0_core_start(start), @@ -54,7 +54,7 @@ module conspiracion done = 0; end - assign data_rw[7:0] = out; + assign data_wr[7:0] = out; assign write = dir; always @(posedge clk_clk) unique case(state) |