summaryrefslogtreecommitdiff
path: root/rtl
diff options
context:
space:
mode:
Diffstat (limited to '')
-rw-r--r--rtl/cache/cache_mem.sv (renamed from rtl/cache/mem.sv)0
-rw-r--r--rtl/cache/cache_monitor.sv (renamed from rtl/cache/monitor.sv)0
-rw-r--r--rtl/cache/cache_offsets.sv (renamed from rtl/cache/offsets.sv)0
-rw-r--r--rtl/cache/cache_ring.sv (renamed from rtl/cache/ring.sv)0
-rw-r--r--rtl/cache/cache_routing.sv (renamed from rtl/cache/routing.sv)0
-rw-r--r--rtl/cache/cache_sram.sv (renamed from rtl/cache/sram.sv)0
-rw-r--r--rtl/cache/cache_token.sv (renamed from rtl/cache/token.sv)0
-rw-r--r--rtl/core/arm810.sv2
-rw-r--r--rtl/core/core_alu.sv (renamed from rtl/core/alu/alu.sv)2
-rw-r--r--rtl/core/core_alu_add.sv (renamed from rtl/core/alu/add.sv)0
-rw-r--r--rtl/core/core_alu_and.sv (renamed from rtl/core/alu/and.sv)0
-rw-r--r--rtl/core/core_alu_orr.sv (renamed from rtl/core/alu/orr.sv)0
-rw-r--r--rtl/core/core_alu_xor.sv (renamed from rtl/core/alu/xor.sv)0
-rw-r--r--rtl/core/core_control.sv (renamed from rtl/core/control/control.sv)0
-rw-r--r--rtl/core/core_control_branch.sv (renamed from rtl/core/control/branch.sv)0
-rw-r--r--rtl/core/core_control_coproc.sv (renamed from rtl/core/control/coproc.sv)0
-rw-r--r--rtl/core/core_control_cycles.sv (renamed from rtl/core/control/cycles.sv)0
-rw-r--r--rtl/core/core_control_data.sv (renamed from rtl/core/control/data.sv)0
-rw-r--r--rtl/core/core_control_debug.sv (renamed from rtl/core/control/debug.sv)0
-rw-r--r--rtl/core/core_control_exception.sv (renamed from rtl/core/control/exception.sv)0
-rw-r--r--rtl/core/core_control_issue.sv (renamed from rtl/core/control/issue.sv)0
-rw-r--r--rtl/core/core_control_ldst.sv (renamed from rtl/core/control/ldst/ldst.sv)0
-rw-r--r--rtl/core/core_control_ldst_pop.sv (renamed from rtl/core/control/ldst/pop.sv)0
-rw-r--r--rtl/core/core_control_ldst_sizes.sv (renamed from rtl/core/control/ldst/sizes.sv)0
-rw-r--r--rtl/core/core_control_mul.sv (renamed from rtl/core/control/mul_fu.sv)0
-rw-r--r--rtl/core/core_control_psr.sv (renamed from rtl/core/control/status.sv)0
-rw-r--r--rtl/core/core_control_select.sv (renamed from rtl/core/control/select.sv)0
-rw-r--r--rtl/core/core_control_stall.sv (renamed from rtl/core/control/stall.sv)0
-rw-r--r--rtl/core/core_control_writeback.sv (renamed from rtl/core/control/writeback.sv)0
-rw-r--r--rtl/core/core_cp15.sv (renamed from rtl/core/cp15/cp15.sv)4
-rw-r--r--rtl/core/core_cp15_cache.sv (renamed from rtl/core/cp15/cache_ops.sv)0
-rw-r--r--rtl/core/core_cp15_cache_lockdown.sv (renamed from rtl/core/cp15/cache_lockdown.sv)0
-rw-r--r--rtl/core/core_cp15_cpuid.sv (renamed from rtl/core/cp15/cpuid.sv)2
-rw-r--r--rtl/core/core_cp15_cyclecnt.sv (renamed from rtl/core/cp15/cyclecnt.sv)0
-rw-r--r--rtl/core/core_cp15_domain.sv (renamed from rtl/core/cp15/domain.sv)0
-rw-r--r--rtl/core/core_cp15_far.sv (renamed from rtl/core/cp15/far.sv)2
-rw-r--r--rtl/core/core_cp15_fsr.sv (renamed from rtl/core/cp15/fsr.sv)4
-rw-r--r--rtl/core/core_cp15_syscfg.sv (renamed from rtl/core/cp15/syscfg.sv)2
-rw-r--r--rtl/core/core_cp15_tlb.sv (renamed from rtl/core/cp15/tlb.sv)0
-rw-r--r--rtl/core/core_cp15_tlb_lockdown.sv (renamed from rtl/core/cp15/tlb_lockdown.sv)0
-rw-r--r--rtl/core/core_cp15_ttbr.sv (renamed from rtl/core/cp15/ttbr.sv)4
-rw-r--r--rtl/core/core_decode.sv (renamed from rtl/core/decode/decode.sv)2
-rw-r--r--rtl/core/core_decode_branch.sv (renamed from rtl/core/decode/branch_dec.sv)2
-rw-r--r--rtl/core/core_decode_coproc.sv (renamed from rtl/core/decode/coproc_dec.sv)2
-rw-r--r--rtl/core/core_decode_data.sv (renamed from rtl/core/decode/data_dec.sv)2
-rw-r--r--rtl/core/core_decode_ldst_addr.sv (renamed from rtl/core/decode/ldst/addr.sv)0
-rw-r--r--rtl/core/core_decode_ldst_exclusive.sv (renamed from rtl/core/decode/ldst/exclusive.sv)2
-rw-r--r--rtl/core/core_decode_ldst_misc.sv (renamed from rtl/core/decode/ldst/misc.sv)2
-rw-r--r--rtl/core/core_decode_ldst_multiple.sv (renamed from rtl/core/decode/ldst/multiple.sv)2
-rw-r--r--rtl/core/core_decode_ldst_single.sv (renamed from rtl/core/decode/ldst/single.sv)2
-rw-r--r--rtl/core/core_decode_mrs.sv (renamed from rtl/core/decode/mrs.sv)2
-rw-r--r--rtl/core/core_decode_msr.sv (renamed from rtl/core/decode/msr.sv)2
-rw-r--r--rtl/core/core_decode_mul.sv (renamed from rtl/core/decode/mul_dec.sv)2
-rw-r--r--rtl/core/core_decode_mux.sv (renamed from rtl/core/decode/mux.sv)2
-rw-r--r--rtl/core/core_decode_snd.sv (renamed from rtl/core/decode/snd.sv)2
-rw-r--r--rtl/core/core_fetch.sv (renamed from rtl/core/fetch/fetch.sv)0
-rw-r--r--rtl/core/core_mmu.sv (renamed from rtl/core/mmu/mmu.sv)2
-rw-r--r--rtl/core/core_mmu_arbiter.sv (renamed from rtl/core/mmu/arbiter.sv)0
-rw-r--r--rtl/core/core_mmu_fault.sv (renamed from rtl/core/mmu/fault.sv)2
-rw-r--r--rtl/core/core_mmu_pagewalk.sv (renamed from rtl/core/mmu/pagewalk.sv)2
-rw-r--r--rtl/core/core_mul.sv (renamed from rtl/core/mul.sv)0
-rw-r--r--rtl/core/core_porch.sv (renamed from rtl/core/porch/porch.sv)0
-rw-r--r--rtl/core/core_porch_conds.sv (renamed from rtl/core/porch/conds.sv)2
-rw-r--r--rtl/core/core_prefetch.sv (renamed from rtl/core/fetch/prefetch.sv)0
-rw-r--r--rtl/core/core_psr.sv (renamed from rtl/core/psr.sv)0
-rw-r--r--rtl/core/core_reg_file.sv (renamed from rtl/core/regs/file.sv)0
-rw-r--r--rtl/core/core_reg_map.sv (renamed from rtl/core/regs/reg_map.sv)0
-rw-r--r--rtl/core/core_regs.sv (renamed from rtl/core/regs/regs.sv)0
-rw-r--r--rtl/core/core_shifter.sv (renamed from rtl/core/shifter.sv)0
-rw-r--r--rtl/core/cp15_map.sv (renamed from rtl/core/cp15/map.sv)0
-rw-r--r--rtl/core/isa.sv (renamed from rtl/core/decode/isa.sv)0
-rw-r--r--rtl/core/mmu_format.sv (renamed from rtl/core/mmu/format.sv)0
-rw-r--r--rtl/perf/perf_link.sv (renamed from rtl/perf/link.sv)0
-rw-r--r--rtl/perf/perf_snoop.sv (renamed from rtl/perf/snoop.sv)0
-rw-r--r--rtl/smp/smp_pe.sv (renamed from rtl/smp/pe.sv)0
75 files changed, 28 insertions, 28 deletions
diff --git a/rtl/cache/mem.sv b/rtl/cache/cache_mem.sv
index a575d0d..a575d0d 100644
--- a/rtl/cache/mem.sv
+++ b/rtl/cache/cache_mem.sv
diff --git a/rtl/cache/monitor.sv b/rtl/cache/cache_monitor.sv
index 380019e..380019e 100644
--- a/rtl/cache/monitor.sv
+++ b/rtl/cache/cache_monitor.sv
diff --git a/rtl/cache/offsets.sv b/rtl/cache/cache_offsets.sv
index 7769394..7769394 100644
--- a/rtl/cache/offsets.sv
+++ b/rtl/cache/cache_offsets.sv
diff --git a/rtl/cache/ring.sv b/rtl/cache/cache_ring.sv
index d934fb7..d934fb7 100644
--- a/rtl/cache/ring.sv
+++ b/rtl/cache/cache_ring.sv
diff --git a/rtl/cache/routing.sv b/rtl/cache/cache_routing.sv
index a0c4347..a0c4347 100644
--- a/rtl/cache/routing.sv
+++ b/rtl/cache/cache_routing.sv
diff --git a/rtl/cache/sram.sv b/rtl/cache/cache_sram.sv
index d63cdad..d63cdad 100644
--- a/rtl/cache/sram.sv
+++ b/rtl/cache/cache_sram.sv
diff --git a/rtl/cache/token.sv b/rtl/cache/cache_token.sv
index cb3e59d..cb3e59d 100644
--- a/rtl/cache/token.sv
+++ b/rtl/cache/cache_token.sv
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index cfe202a..66493e2 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -1,4 +1,4 @@
-`include "core/mmu/format.sv"
+`include "core/mmu_format.sv"
`include "core/uarch.sv"
module arm810
diff --git a/rtl/core/alu/alu.sv b/rtl/core/core_alu.sv
index c0ccd32..6dafa65 100644
--- a/rtl/core/alu/alu.sv
+++ b/rtl/core/core_alu.sv
@@ -1,5 +1,5 @@
+`include "core/isa.sv"
`include "core/uarch.sv"
-`include "core/decode/isa.sv"
module core_alu
#(parameter W=16)
diff --git a/rtl/core/alu/add.sv b/rtl/core/core_alu_add.sv
index a15a6b6..a15a6b6 100644
--- a/rtl/core/alu/add.sv
+++ b/rtl/core/core_alu_add.sv
diff --git a/rtl/core/alu/and.sv b/rtl/core/core_alu_and.sv
index d119f24..d119f24 100644
--- a/rtl/core/alu/and.sv
+++ b/rtl/core/core_alu_and.sv
diff --git a/rtl/core/alu/orr.sv b/rtl/core/core_alu_orr.sv
index 1ee87c2..1ee87c2 100644
--- a/rtl/core/alu/orr.sv
+++ b/rtl/core/core_alu_orr.sv
diff --git a/rtl/core/alu/xor.sv b/rtl/core/core_alu_xor.sv
index f55dfc2..f55dfc2 100644
--- a/rtl/core/alu/xor.sv
+++ b/rtl/core/core_alu_xor.sv
diff --git a/rtl/core/control/control.sv b/rtl/core/core_control.sv
index 27be940..27be940 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/core_control.sv
diff --git a/rtl/core/control/branch.sv b/rtl/core/core_control_branch.sv
index 0298b95..0298b95 100644
--- a/rtl/core/control/branch.sv
+++ b/rtl/core/core_control_branch.sv
diff --git a/rtl/core/control/coproc.sv b/rtl/core/core_control_coproc.sv
index 05ac655..05ac655 100644
--- a/rtl/core/control/coproc.sv
+++ b/rtl/core/core_control_coproc.sv
diff --git a/rtl/core/control/cycles.sv b/rtl/core/core_control_cycles.sv
index 772697d..772697d 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/core_control_cycles.sv
diff --git a/rtl/core/control/data.sv b/rtl/core/core_control_data.sv
index 3174ee1..3174ee1 100644
--- a/rtl/core/control/data.sv
+++ b/rtl/core/core_control_data.sv
diff --git a/rtl/core/control/debug.sv b/rtl/core/core_control_debug.sv
index 35b1334..35b1334 100644
--- a/rtl/core/control/debug.sv
+++ b/rtl/core/core_control_debug.sv
diff --git a/rtl/core/control/exception.sv b/rtl/core/core_control_exception.sv
index 387e9c1..387e9c1 100644
--- a/rtl/core/control/exception.sv
+++ b/rtl/core/core_control_exception.sv
diff --git a/rtl/core/control/issue.sv b/rtl/core/core_control_issue.sv
index 5bd03e1..5bd03e1 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/core_control_issue.sv
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/core_control_ldst.sv
index aa5c957..aa5c957 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/core_control_ldst.sv
diff --git a/rtl/core/control/ldst/pop.sv b/rtl/core/core_control_ldst_pop.sv
index 64dc04d..64dc04d 100644
--- a/rtl/core/control/ldst/pop.sv
+++ b/rtl/core/core_control_ldst_pop.sv
diff --git a/rtl/core/control/ldst/sizes.sv b/rtl/core/core_control_ldst_sizes.sv
index dff4662..dff4662 100644
--- a/rtl/core/control/ldst/sizes.sv
+++ b/rtl/core/core_control_ldst_sizes.sv
diff --git a/rtl/core/control/mul_fu.sv b/rtl/core/core_control_mul.sv
index 8352435..8352435 100644
--- a/rtl/core/control/mul_fu.sv
+++ b/rtl/core/core_control_mul.sv
diff --git a/rtl/core/control/status.sv b/rtl/core/core_control_psr.sv
index 6616bc9..6616bc9 100644
--- a/rtl/core/control/status.sv
+++ b/rtl/core/core_control_psr.sv
diff --git a/rtl/core/control/select.sv b/rtl/core/core_control_select.sv
index dc04282..dc04282 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/core_control_select.sv
diff --git a/rtl/core/control/stall.sv b/rtl/core/core_control_stall.sv
index 02a7552..02a7552 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/core_control_stall.sv
diff --git a/rtl/core/control/writeback.sv b/rtl/core/core_control_writeback.sv
index 027a7d7..027a7d7 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/core_control_writeback.sv
diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/core_cp15.sv
index 5a482d4..09b899a 100644
--- a/rtl/core/cp15/cp15.sv
+++ b/rtl/core/core_cp15.sv
@@ -1,5 +1,5 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
+`include "core/cp15_map.sv"
+`include "core/mmu_format.sv"
`include "core/uarch.sv"
module core_cp15
diff --git a/rtl/core/cp15/cache_ops.sv b/rtl/core/core_cp15_cache.sv
index cb6d4ad..cb6d4ad 100644
--- a/rtl/core/cp15/cache_ops.sv
+++ b/rtl/core/core_cp15_cache.sv
diff --git a/rtl/core/cp15/cache_lockdown.sv b/rtl/core/core_cp15_cache_lockdown.sv
index 65d4c0f..65d4c0f 100644
--- a/rtl/core/cp15/cache_lockdown.sv
+++ b/rtl/core/core_cp15_cache_lockdown.sv
diff --git a/rtl/core/cp15/cpuid.sv b/rtl/core/core_cp15_cpuid.sv
index c9cab59..6e23c7e 100644
--- a/rtl/core/cp15/cpuid.sv
+++ b/rtl/core/core_cp15_cpuid.sv
@@ -1,5 +1,5 @@
`include "core/uarch.sv"
-`include "core/cp15/map.sv"
+`include "core/cp15_map.sv"
module core_cp15_cpuid
(
diff --git a/rtl/core/cp15/cyclecnt.sv b/rtl/core/core_cp15_cyclecnt.sv
index b079a1b..b079a1b 100644
--- a/rtl/core/cp15/cyclecnt.sv
+++ b/rtl/core/core_cp15_cyclecnt.sv
diff --git a/rtl/core/cp15/domain.sv b/rtl/core/core_cp15_domain.sv
index de37de4..de37de4 100644
--- a/rtl/core/cp15/domain.sv
+++ b/rtl/core/core_cp15_domain.sv
diff --git a/rtl/core/cp15/far.sv b/rtl/core/core_cp15_far.sv
index 36e76db..ca1dcf1 100644
--- a/rtl/core/cp15/far.sv
+++ b/rtl/core/core_cp15_far.sv
@@ -1,5 +1,5 @@
`include "core/uarch.sv"
-`include "core/cp15/map.sv"
+`include "core/cp15_map.sv"
module core_cp15_far
(
diff --git a/rtl/core/cp15/fsr.sv b/rtl/core/core_cp15_fsr.sv
index 81b4992..b388d00 100644
--- a/rtl/core/cp15/fsr.sv
+++ b/rtl/core/core_cp15_fsr.sv
@@ -1,5 +1,5 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
+`include "core/cp15_map.sv"
+`include "core/mmu_format.sv"
`include "core/uarch.sv"
module core_cp15_fsr
diff --git a/rtl/core/cp15/syscfg.sv b/rtl/core/core_cp15_syscfg.sv
index 5bd2530..cdd6014 100644
--- a/rtl/core/cp15/syscfg.sv
+++ b/rtl/core/core_cp15_syscfg.sv
@@ -1,5 +1,5 @@
`include "core/uarch.sv"
-`include "core/cp15/map.sv"
+`include "core/cp15_map.sv"
module core_cp15_syscfg
(
diff --git a/rtl/core/cp15/tlb.sv b/rtl/core/core_cp15_tlb.sv
index 5cbd19d..5cbd19d 100644
--- a/rtl/core/cp15/tlb.sv
+++ b/rtl/core/core_cp15_tlb.sv
diff --git a/rtl/core/cp15/tlb_lockdown.sv b/rtl/core/core_cp15_tlb_lockdown.sv
index 1972c33..1972c33 100644
--- a/rtl/core/cp15/tlb_lockdown.sv
+++ b/rtl/core/core_cp15_tlb_lockdown.sv
diff --git a/rtl/core/cp15/ttbr.sv b/rtl/core/core_cp15_ttbr.sv
index b462955..3b1a76a 100644
--- a/rtl/core/cp15/ttbr.sv
+++ b/rtl/core/core_cp15_ttbr.sv
@@ -1,5 +1,5 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
+`include "core/cp15_map.sv"
+`include "core/mmu_format.sv"
`include "core/uarch.sv"
module core_cp15_ttbr
diff --git a/rtl/core/decode/decode.sv b/rtl/core/core_decode.sv
index 219f975..b43c239 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/core_decode.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode
diff --git a/rtl/core/decode/branch_dec.sv b/rtl/core/core_decode_branch.sv
index 1dbc1ad..9916374 100644
--- a/rtl/core/decode/branch_dec.sv
+++ b/rtl/core/core_decode_branch.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_branch
diff --git a/rtl/core/decode/coproc_dec.sv b/rtl/core/core_decode_coproc.sv
index 153cadf..c9a68c7 100644
--- a/rtl/core/decode/coproc_dec.sv
+++ b/rtl/core/core_decode_coproc.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_coproc
diff --git a/rtl/core/decode/data_dec.sv b/rtl/core/core_decode_data.sv
index f744972..a4e993e 100644
--- a/rtl/core/decode/data_dec.sv
+++ b/rtl/core/core_decode_data.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_data
diff --git a/rtl/core/decode/ldst/addr.sv b/rtl/core/core_decode_ldst_addr.sv
index 345f0ea..345f0ea 100644
--- a/rtl/core/decode/ldst/addr.sv
+++ b/rtl/core/core_decode_ldst_addr.sv
diff --git a/rtl/core/decode/ldst/exclusive.sv b/rtl/core/core_decode_ldst_exclusive.sv
index 7942a04..f45cbfa 100644
--- a/rtl/core/decode/ldst/exclusive.sv
+++ b/rtl/core/core_decode_ldst_exclusive.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_ldst_exclusive
diff --git a/rtl/core/decode/ldst/misc.sv b/rtl/core/core_decode_ldst_misc.sv
index 72d648c..bedbdf4 100644
--- a/rtl/core/decode/ldst/misc.sv
+++ b/rtl/core/core_decode_ldst_misc.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_ldst_misc
diff --git a/rtl/core/decode/ldst/multiple.sv b/rtl/core/core_decode_ldst_multiple.sv
index c822ab0..234bd56 100644
--- a/rtl/core/decode/ldst/multiple.sv
+++ b/rtl/core/core_decode_ldst_multiple.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_ldst_multiple
diff --git a/rtl/core/decode/ldst/single.sv b/rtl/core/core_decode_ldst_single.sv
index af096a7..0f47a30 100644
--- a/rtl/core/decode/ldst/single.sv
+++ b/rtl/core/core_decode_ldst_single.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_ldst_single
diff --git a/rtl/core/decode/mrs.sv b/rtl/core/core_decode_mrs.sv
index 05018cd..8e4b19b 100644
--- a/rtl/core/decode/mrs.sv
+++ b/rtl/core/core_decode_mrs.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_mrs
diff --git a/rtl/core/decode/msr.sv b/rtl/core/core_decode_msr.sv
index c3f0e3d..3f10255 100644
--- a/rtl/core/decode/msr.sv
+++ b/rtl/core/core_decode_msr.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_msr
diff --git a/rtl/core/decode/mul_dec.sv b/rtl/core/core_decode_mul.sv
index 114b65b..88cc422 100644
--- a/rtl/core/decode/mul_dec.sv
+++ b/rtl/core/core_decode_mul.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_mul
diff --git a/rtl/core/decode/mux.sv b/rtl/core/core_decode_mux.sv
index 6f0451a..f90ee49 100644
--- a/rtl/core/decode/mux.sv
+++ b/rtl/core/core_decode_mux.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_mux
diff --git a/rtl/core/decode/snd.sv b/rtl/core/core_decode_snd.sv
index 264982e..3ee8722 100644
--- a/rtl/core/decode/snd.sv
+++ b/rtl/core/core_decode_snd.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_decode_snd
diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/core_fetch.sv
index 279d2c2..279d2c2 100644
--- a/rtl/core/fetch/fetch.sv
+++ b/rtl/core/core_fetch.sv
diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/core_mmu.sv
index 22dfc3b..3060d69 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/core_mmu.sv
@@ -1,4 +1,4 @@
-`include "core/mmu/format.sv"
+`include "core/mmu_format.sv"
`include "core/uarch.sv"
module core_mmu
diff --git a/rtl/core/mmu/arbiter.sv b/rtl/core/core_mmu_arbiter.sv
index b0da7c8..b0da7c8 100644
--- a/rtl/core/mmu/arbiter.sv
+++ b/rtl/core/core_mmu_arbiter.sv
diff --git a/rtl/core/mmu/fault.sv b/rtl/core/core_mmu_fault.sv
index b33cec2..ec80753 100644
--- a/rtl/core/mmu/fault.sv
+++ b/rtl/core/core_mmu_fault.sv
@@ -1,4 +1,4 @@
-`include "core/mmu/format.sv"
+`include "core/mmu_format.sv"
`include "core/uarch.sv"
module core_mmu_fault
diff --git a/rtl/core/mmu/pagewalk.sv b/rtl/core/core_mmu_pagewalk.sv
index 70c932c..bdf1989 100644
--- a/rtl/core/mmu/pagewalk.sv
+++ b/rtl/core/core_mmu_pagewalk.sv
@@ -1,4 +1,4 @@
-`include "core/mmu/format.sv"
+`include "core/mmu_format.sv"
`include "core/uarch.sv"
module core_mmu_pagewalk
diff --git a/rtl/core/mul.sv b/rtl/core/core_mul.sv
index 19bbb9a..19bbb9a 100644
--- a/rtl/core/mul.sv
+++ b/rtl/core/core_mul.sv
diff --git a/rtl/core/porch/porch.sv b/rtl/core/core_porch.sv
index 060ab91..060ab91 100644
--- a/rtl/core/porch/porch.sv
+++ b/rtl/core/core_porch.sv
diff --git a/rtl/core/porch/conds.sv b/rtl/core/core_porch_conds.sv
index b8db1e7..3d00e12 100644
--- a/rtl/core/porch/conds.sv
+++ b/rtl/core/core_porch_conds.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
`include "core/uarch.sv"
module core_porch_conds
diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/core_prefetch.sv
index 719ad95..719ad95 100644
--- a/rtl/core/fetch/prefetch.sv
+++ b/rtl/core/core_prefetch.sv
diff --git a/rtl/core/psr.sv b/rtl/core/core_psr.sv
index 7bbffe6..7bbffe6 100644
--- a/rtl/core/psr.sv
+++ b/rtl/core/core_psr.sv
diff --git a/rtl/core/regs/file.sv b/rtl/core/core_reg_file.sv
index 2ba95e8..2ba95e8 100644
--- a/rtl/core/regs/file.sv
+++ b/rtl/core/core_reg_file.sv
diff --git a/rtl/core/regs/reg_map.sv b/rtl/core/core_reg_map.sv
index 11085d4..11085d4 100644
--- a/rtl/core/regs/reg_map.sv
+++ b/rtl/core/core_reg_map.sv
diff --git a/rtl/core/regs/regs.sv b/rtl/core/core_regs.sv
index f9cecad..f9cecad 100644
--- a/rtl/core/regs/regs.sv
+++ b/rtl/core/core_regs.sv
diff --git a/rtl/core/shifter.sv b/rtl/core/core_shifter.sv
index 96b8866..96b8866 100644
--- a/rtl/core/shifter.sv
+++ b/rtl/core/core_shifter.sv
diff --git a/rtl/core/cp15/map.sv b/rtl/core/cp15_map.sv
index 438a5bf..438a5bf 100644
--- a/rtl/core/cp15/map.sv
+++ b/rtl/core/cp15_map.sv
diff --git a/rtl/core/decode/isa.sv b/rtl/core/isa.sv
index 6784eca..6784eca 100644
--- a/rtl/core/decode/isa.sv
+++ b/rtl/core/isa.sv
diff --git a/rtl/core/mmu/format.sv b/rtl/core/mmu_format.sv
index 3029b83..3029b83 100644
--- a/rtl/core/mmu/format.sv
+++ b/rtl/core/mmu_format.sv
diff --git a/rtl/perf/link.sv b/rtl/perf/perf_link.sv
index 323af45..323af45 100644
--- a/rtl/perf/link.sv
+++ b/rtl/perf/perf_link.sv
diff --git a/rtl/perf/snoop.sv b/rtl/perf/perf_snoop.sv
index e98153e..e98153e 100644
--- a/rtl/perf/snoop.sv
+++ b/rtl/perf/perf_snoop.sv
diff --git a/rtl/smp/pe.sv b/rtl/smp/smp_pe.sv
index 5c675ee..5c675ee 100644
--- a/rtl/smp/pe.sv
+++ b/rtl/smp/smp_pe.sv