diff options
Diffstat (limited to '')
| -rw-r--r-- | rtl/gfx/gfx.sv | 5 | ||||
| -rw-r--r-- | rtl/gfx/gfx_sp.sv | 33 | ||||
| -rw-r--r-- | rtl/gfx/gfx_sp_batch.sv | 2 | ||||
| -rw-r--r-- | rtl/gfx/gfx_sp_combiner.sv | 2 | ||||
| -rw-r--r-- | rtl/gfx/gfx_sp_shuffler.sv | 2 | ||||
| -rw-r--r-- | rtl/gfx/gfx_sp_stream.sv | 66 |
6 files changed, 101 insertions, 9 deletions
diff --git a/rtl/gfx/gfx.sv b/rtl/gfx/gfx.sv index 4837b8e..e88dc56 100644 --- a/rtl/gfx/gfx.sv +++ b/rtl/gfx/gfx.sv @@ -43,11 +43,14 @@ module gfx .* ); - logic batch_read, fetch_read; + logic batch_read, fetch_read, send_valid; + lane_word send_data; + lane_mask send_mask; vram_addr batch_address, fetch_address; gfx_sp sp ( + .send_ready(1), //TODO .* ); diff --git a/rtl/gfx/gfx_sp.sv b/rtl/gfx/gfx_sp.sv index acb1dc2..ea3b126 100644 --- a/rtl/gfx/gfx_sp.sv +++ b/rtl/gfx/gfx_sp.sv @@ -19,7 +19,12 @@ module gfx_sp input logic program_start, input cmd_word program_header_base, - program_header_size + program_header_size, + + input logic send_ready, + output logic send_valid, + output lane_word send_data, + output lane_mask send_mask ); logic batch_start, clear_lanes, insn_valid, running; @@ -42,12 +47,16 @@ module gfx_sp .* ); + logic recv_valid; + lane_word recv_data; + lane_mask recv_mask; + gfx_sp_batch batch ( - .out_data(), - .out_mask(), - .out_ready(1), - .out_valid(), + .out_data(recv_data), + .out_mask(recv_mask), + .out_ready(recv_ready), + .out_valid(recv_valid), .* ); @@ -77,6 +86,20 @@ module gfx_sp .* ); + logic recv_ready; + + gfx_sp_stream stream + ( + .a(), + .wb(), + .deco(), + .in_ready(), + .in_valid(0), + .wb_ready(1), + .wb_valid(), + .* + ); + logic batch_end, deco_ready; assign deco_ready = 1; diff --git a/rtl/gfx/gfx_sp_batch.sv b/rtl/gfx/gfx_sp_batch.sv index a2c13ee..b999219 100644 --- a/rtl/gfx/gfx_sp_batch.sv +++ b/rtl/gfx/gfx_sp_batch.sv @@ -15,8 +15,8 @@ module gfx_sp_batch input vram_insn_addr batch_base, input cmd_word batch_length, - output lane_word out_data, output lane_mask out_mask, + output lane_word out_data, input logic out_ready, output logic out_valid ); diff --git a/rtl/gfx/gfx_sp_combiner.sv b/rtl/gfx/gfx_sp_combiner.sv index e5e64c3..8f16cd3 100644 --- a/rtl/gfx/gfx_sp_combiner.sv +++ b/rtl/gfx/gfx_sp_combiner.sv @@ -5,9 +5,9 @@ module gfx_sp_combiner input logic clk, rst_n, - input insn_deco deco, input mat4 a, b, + input insn_deco deco, input logic in_valid, output logic in_ready, diff --git a/rtl/gfx/gfx_sp_shuffler.sv b/rtl/gfx/gfx_sp_shuffler.sv index 627bf8a..8e1e461 100644 --- a/rtl/gfx/gfx_sp_shuffler.sv +++ b/rtl/gfx/gfx_sp_shuffler.sv @@ -5,9 +5,9 @@ module gfx_sp_shuffler input logic clk, rst_n, - input insn_deco deco, input mat4 a, b, + input insn_deco deco, input logic in_valid, output logic in_ready, diff --git a/rtl/gfx/gfx_sp_stream.sv b/rtl/gfx/gfx_sp_stream.sv new file mode 100644 index 0000000..fed8021 --- /dev/null +++ b/rtl/gfx/gfx_sp_stream.sv @@ -0,0 +1,66 @@ +`include "gfx/gfx_defs.sv" + +module gfx_sp_stream +( + input logic clk, + rst_n, + + input mat4 a, + input insn_deco deco, + input logic in_valid, + output logic in_ready, + + output wb_op wb, + input logic wb_ready, + output logic wb_valid, + + input lane_word recv_data, + input lane_mask recv_mask, + input logic recv_valid, + output logic recv_ready, + + input logic send_ready, + output logic send_valid, + output lane_word send_data, + output lane_mask send_mask +); + + logic active, recv; + vreg_num wb_reg; + + assign in_ready = !active; + assign recv_ready = active && recv && wb_ready; + + assign wb_valid = active && recv && recv_valid; + assign send_valid = active && !recv; + + assign wb.dst = wb_reg; + assign wb.data = recv_data; + + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) begin + active <= 0; + send_mask <= 0; + end else begin + if (!active) + active <= in_valid && (deco.writeback || |send_mask); + else if (recv) + active <= !wb_ready || !recv_valid; + else + active <= !send_ready; + + if (recv_ready && recv_valid) + send_mask <= send_mask & recv_mask; + + if (in_ready && in_valid && deco.clear_lanes) + send_mask <= {($bits(send_mask)){1'b1}}; + end + + always_ff @(posedge clk) + if (!active) begin + recv <= deco.writeback; + wb_reg <= deco.dst; + send_data <= a; + end + +endmodule |