diff options
Diffstat (limited to '')
| -rw-r--r-- | rtl/top/decode_test.sv | 14 | ||||
| -rw-r--r-- | rtl/top/fetch_test.sv | 25 | ||||
| -rw-r--r-- | rtl/top/hps_sdram_test.sv | 93 | ||||
| -rw-r--r-- | rtl/top/mul_test.sv | 33 | ||||
| -rw-r--r-- | rtl/top/smp_sim.sv | 35 |
5 files changed, 35 insertions, 165 deletions
diff --git a/rtl/top/decode_test.sv b/rtl/top/decode_test.sv deleted file mode 100644 index 91962ea..0000000 --- a/rtl/top/decode_test.sv +++ /dev/null @@ -1,14 +0,0 @@ -`timescale 1 ns / 1 ps -`include "core/decode/isa.sv" -`include "core/uarch.sv" - -module decode_test -( - input word insn, - - output insn_decode dec -); - - core_decode DUT (.*); - -endmodule diff --git a/rtl/top/fetch_test.sv b/rtl/top/fetch_test.sv deleted file mode 100644 index 4ab5fd1..0000000 --- a/rtl/top/fetch_test.sv +++ /dev/null @@ -1,25 +0,0 @@ -`timescale 1 ns / 1 ps -`include "core/uarch.sv" - -module fetch_test -( - input logic clk, - stall, - branch, - prefetch_flush, - fetched, - wr_pc, - input ptr branch_target, - input word wr_current, - fetch_data, - - output logic fetch, - output word insn, - output ptr insn_pc, - addr - -); - - core_fetch #(.PREFETCH_ORDER(3)) DUT (.flush(), .*); - -endmodule diff --git a/rtl/top/hps_sdram_test.sv b/rtl/top/hps_sdram_test.sv deleted file mode 100644 index 28d6175..0000000 --- a/rtl/top/hps_sdram_test.sv +++ /dev/null @@ -1,93 +0,0 @@ -module hps_sdram_test -( - input wire clk_clk, - output wire [12:0] memory_mem_a, - output wire [2:0] memory_mem_ba, - output wire memory_mem_ck, - output wire memory_mem_ck_n, - output wire memory_mem_cke, - output wire memory_mem_cs_n, - output wire memory_mem_ras_n, - output wire memory_mem_cas_n, - output wire memory_mem_we_n, - output wire memory_mem_reset_n, - inout wire [7:0] memory_mem_dq, - inout wire memory_mem_dqs, - inout wire memory_mem_dqs_n, - output wire memory_mem_odt, - output wire memory_mem_dm, - input wire memory_oct_rzqin, - /*input wire reset_reset_n,*/ - - input logic dir, clr, mov, add, io, - output logic[7:0] out, - output logic done -); - - wire reset_reset_n; - assign reset_reset_n = 1'b1; - - enum { - IDLE, - IO, - RELEASE - } state; - - logic[29:0] addr; - logic[31:0] data_rd, data_wr; - logic ready, write, start; - - logic [7:0] leds; - - platform plat - ( - .master_0_core_addr(addr), - .master_0_core_data_rd(data_rd), - .master_0_core_data_wr(data_wr), - .master_0_core_ready(ready), - .master_0_core_write(write), - .master_0_core_start(start), - .* - ); - - initial begin - addr = 0; - start = 0; - state = IDLE; - done = 0; - end - - assign data_wr[7:0] = out; - assign write = dir; - - always_ff @(posedge clk_clk) unique case(state) - IDLE: begin - state <= RELEASE; - - if(~clr) - out <= 0; - else if(~mov) - addr <= dir ? addr + 1 : addr - 1; - else if(~add) - out <= dir ? out + 1 : out - 1; - else if(~io) begin - start <= 1; - state <= IO; - end - end - - IO: begin - done <= 1; - start <= 0; - if(ready) begin - if(~dir) out <= data_rd[7:0]; - state <= RELEASE; - end - end - - RELEASE: begin - done <= ~io; - if(clr & mov & add & io) state <= IDLE; - end - endcase -endmodule diff --git a/rtl/top/mul_test.sv b/rtl/top/mul_test.sv deleted file mode 100644 index 1395772..0000000 --- a/rtl/top/mul_test.sv +++ /dev/null @@ -1,33 +0,0 @@ -`timescale 1 ns / 1 ps - -module mul_test -#(parameter U=32) -( - input logic[U - 1:0] a, // primer sumando - b, // segundo sumando - input logic[U - 1:0] c_hi, // parte más significativa de c - c_lo, // parte menos significativa de c - input logic c_size, // 1 si c es de 2 words, cualquier otro valor si c es de 1 word - clk, // clock, ya que es una máquina de estados - rst, // reset - add, // 1 si c se suma - sig, // 1 si a y b son signed - q_size, // 1 si q es de 2 words, cualquier otro valor si es de 1 word - start, // 1 indica que se inicie la multiplicacion - - output logic [U - 1:0] q_hi, // parte más significativa del resultado - output logic [U - 1:0] q_lo, // parte menos significativa del resultado - output logic [2*U-1:0] result, - output logic n, // no hay C ni V, ya que se dejan unaffected - z, - q_sig, // 1 si q es signed, cualquier otro valor si es unsigned - rdy // 1 cuando la multiplicación está lista - - -); - core_mul #(.U(U)) DUT (.*); - -endmodule - - - diff --git a/rtl/top/smp_sim.sv b/rtl/top/smp_sim.sv new file mode 100644 index 0000000..137021c --- /dev/null +++ b/rtl/top/smp_sim.sv @@ -0,0 +1,35 @@ +module smp_sim +( + input logic clk, + rst_n, + + input logic avl_read, + avl_write, + input logic[31:0] avl_writedata, + output logic[31:0] avl_readdata, + + input logic cpu_halted_0, + cpu_halted_1, + cpu_halted_2, + cpu_halted_3, + input logic breakpoint_0, + breakpoint_1, + breakpoint_2, + breakpoint_3, + + output logic halt_0, + halt_1, + halt_2, + halt_3, + step_0, + step_1, + step_2, + step_3 +); + + smp_ctrl dut + ( + .* + ); + +endmodule |