diff options
Diffstat (limited to 'rtl/core')
| -rw-r--r-- | rtl/core/arm810.sv | 29 | ||||
| -rw-r--r-- | rtl/core/control/control.sv | 1 | ||||
| -rw-r--r-- | rtl/core/control/ldst/ldst.sv | 3 | ||||
| -rw-r--r-- | rtl/core/mmu/arbiter.sv | 52 | ||||
| -rw-r--r-- | rtl/core/mmu/mmu.sv | 38 |
5 files changed, 69 insertions, 54 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index ce29821..89f84ec 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -2,18 +2,19 @@ module arm810 ( - input logic clk, - rst_n, - irq, - halt, - - output ptr bus_addr, - output logic bus_start, - bus_write, - input logic bus_ready, - input word bus_data_rd, - output word bus_data_wr, - output logic halted + input logic clk, + rst_n, + irq, + halt, + + output ptr bus_addr, + output logic bus_start, + bus_write, + input logic bus_ready, + input word bus_data_rd, + output word bus_data_wr, + output logic[3:0] bus_data_be, + output logic halted ); ptr fetch_insn_pc, fetch_head, insn_addr; @@ -72,6 +73,7 @@ module arm810 .mem_ready(data_ready), .mem_data_rd(data_data_rd), .mem_data_wr(data_data_wr), + .mem_data_be(data_data_be), .* ); @@ -160,8 +162,9 @@ module arm810 ); ptr data_addr; - logic data_start, data_write, data_ready, insn_ready; word data_data_rd, data_data_wr, insn_data_rd; + logic data_start, data_write, data_ready, insn_ready; + logic[3:0] data_data_be; core_mmu mmu ( diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index adfe9f7..4bff86e 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -47,6 +47,7 @@ module core_control output logic[7:0] shifter_shift, output ptr mem_addr, output word mem_data_wr, + output logic[3:0] mem_data_be, output logic mem_start, mem_write, output word mul_a, diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv index 02f7b4a..dd5155a 100644 --- a/rtl/core/control/ldst/ldst.sv +++ b/rtl/core/control/ldst/ldst.sv @@ -18,6 +18,7 @@ module core_control_ldst alu_b, output ptr mem_addr, + output logic[3:0] mem_data_be, output word mem_data_wr, mem_offset, output logic mem_start, @@ -57,7 +58,7 @@ module core_control_ldst .read(ldst_read), .shift(ldst_shift), .fault(), //TODO: alignment check - .byteenable(), //TODO + .byteenable(mem_data_be), .* ); diff --git a/rtl/core/mmu/arbiter.sv b/rtl/core/mmu/arbiter.sv index 3740539..5a75ddf 100644 --- a/rtl/core/mmu/arbiter.sv +++ b/rtl/core/mmu/arbiter.sv @@ -1,25 +1,27 @@ module core_mmu_arbiter ( - input logic clk, - rst_n, - - input logic bus_ready, - input word bus_data_rd, - data_data_wr, - input ptr insn_addr, - data_addr, - input logic insn_start, - data_start, - data_write, - - output word bus_data_wr, - output ptr bus_addr, - output logic bus_start, - bus_write, - insn_ready, - data_ready, - output word insn_data_rd, - data_data_rd + input logic clk, + rst_n, + + input logic bus_ready, + input word bus_data_rd, + data_data_wr, + input ptr insn_addr, + data_addr, + input logic insn_start, + data_start, + data_write, + input logic[3:0] data_data_be, + + output word bus_data_wr, + output logic[3:0] bus_data_be, + output ptr bus_addr, + output logic bus_start, + bus_write, + insn_ready, + data_ready, + output word insn_data_rd, + data_data_rd ); enum int unsigned @@ -31,6 +33,7 @@ module core_mmu_arbiter ptr hold_addr; word hold_data_wr; logic active, hold_start, hold_write, hold_issue, hold_free, transition; + logic[3:0] hold_data_be; assign insn_data_rd = bus_data_rd; assign data_data_rd = bus_data_rd; @@ -56,19 +59,20 @@ module core_mmu_arbiter DATA: data_ready = bus_ready; endcase + bus_data_wr = data_data_wr; unique case(next_master) INSN: begin bus_addr = insn_addr; bus_write = 0; bus_start = insn_start; - bus_data_wr = {32{1'bx}}; + bus_data_be = 4'b1111; end DATA: begin bus_addr = data_addr; bus_write = data_write; bus_start = data_start; - bus_data_wr = data_data_wr; + bus_data_be = data_data_be; end endcase @@ -77,6 +81,7 @@ module core_mmu_arbiter bus_write = hold_write; bus_start = 1; bus_data_wr = hold_data_wr; + bus_data_be = hold_data_be; end end @@ -89,6 +94,7 @@ module core_mmu_arbiter hold_start <= 0; hold_write <= 0; hold_data_wr <= 0; + hold_data_be <= 0; end else begin master <= next_master; active <= bus_start || (active && !bus_ready); @@ -100,12 +106,14 @@ module core_mmu_arbiter hold_start <= data_start; hold_write <= data_write; hold_data_wr <= data_data_wr; + hold_data_be <= data_data_be; end DATA: begin hold_addr <= insn_addr; hold_start <= insn_start; hold_write <= 0; + hold_data_be <= 4'b1111; end endcase end diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv index a4be70e..a909537 100644 --- a/rtl/core/mmu/mmu.sv +++ b/rtl/core/mmu/mmu.sv @@ -1,25 +1,27 @@ module core_mmu ( - input logic clk, - rst_n, + input logic clk, + rst_n, - input logic bus_ready, - input word bus_data_rd, - data_data_wr, - input ptr insn_addr, - data_addr, - input logic insn_start, - data_start, - data_write, + input logic bus_ready, + input word bus_data_rd, + data_data_wr, + input ptr insn_addr, + data_addr, + input logic insn_start, + data_start, + data_write, + input logic[3:0] data_data_be, - output word bus_data_wr, - output ptr bus_addr, - output logic bus_start, - bus_write, - insn_ready, - data_ready, - output word insn_data_rd, - data_data_rd + output word bus_data_wr, + output logic[3:0] bus_data_be, + output ptr bus_addr, + output logic bus_start, + bus_write, + insn_ready, + data_ready, + output word insn_data_rd, + data_data_rd ); //TODO |