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-rw-r--r--rtl/core/arm810.sv1
-rw-r--r--rtl/core/control/branch.sv22
-rw-r--r--rtl/core/control/control.sv2
-rw-r--r--rtl/core/control/coproc.sv10
-rw-r--r--rtl/core/control/cycles.sv8
-rw-r--r--rtl/core/control/data.sv23
-rw-r--r--rtl/core/control/exception.sv1
-rw-r--r--rtl/core/control/issue.sv15
-rw-r--r--rtl/core/control/ldst/ldst.sv29
-rw-r--r--rtl/core/control/mul.sv64
-rw-r--r--rtl/core/control/select.sv26
-rw-r--r--rtl/core/control/stall.sv8
-rw-r--r--rtl/core/control/writeback.sv86
-rw-r--r--rtl/core/cp15/cp15.sv1
-rw-r--r--rtl/core/fetch/fetch.sv18
-rw-r--r--rtl/core/fetch/prefetch.sv50
-rw-r--r--rtl/core/mmu/mmu.sv60
-rw-r--r--rtl/core/mul.sv13
-rw-r--r--rtl/core/porch/porch.sv15
-rw-r--r--rtl/core/psr.sv72
-rw-r--r--rtl/core/regs/file.sv25
-rw-r--r--rtl/core/regs/regs.sv21
22 files changed, 285 insertions, 285 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 07a397b..ead6f94 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -3,6 +3,7 @@
module arm810
(
input logic clk,
+ rst_n,
irq,
output ptr bus_addr,
diff --git a/rtl/core/control/branch.sv b/rtl/core/control/branch.sv
index 59a4f54..96e6e65 100644
--- a/rtl/core/control/branch.sv
+++ b/rtl/core/control/branch.sv
@@ -3,6 +3,7 @@
module core_control_branch
(
input logic clk,
+ rst_n,
input insn_decode dec,
@@ -14,17 +15,16 @@ module core_control_branch
output ptr branch_target
);
- always_ff @(posedge clk) begin
- branch <= 0;
- if(next_cycle == ISSUE && issue) begin
- branch <= dec.ctrl.branch;
- branch_target <= next_pc_visible + dec.branch.offset;
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ branch <= 1;
+ branch_target <= {$bits(branch_target){1'b0}};
+ end else begin
+ branch <= 0;
+ if(next_cycle == ISSUE && issue) begin
+ branch <= dec.ctrl.branch;
+ branch_target <= next_pc_visible + dec.branch.offset;
+ end
end
- end
-
- initial begin
- branch = 1;
- branch_target = {$bits(branch_target){1'b0}};
- end
endmodule
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 077ba1c..45e8e10 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -3,6 +3,8 @@
module core_control
(
input logic clk,
+ rst_n,
+
input insn_decode dec,
input ptr insn_pc,
input psr_flags flags,
diff --git a/rtl/core/control/coproc.sv b/rtl/core/control/coproc.sv
index b0c8bea..a457b0f 100644
--- a/rtl/core/control/coproc.sv
+++ b/rtl/core/control/coproc.sv
@@ -3,6 +3,7 @@
module core_control_coproc
(
input logic clk,
+ rst_n,
input insn_decode dec,
@@ -12,11 +13,10 @@ module core_control_coproc
output logic coproc
);
- always_ff @(posedge clk)
- if(next_cycle == ISSUE && issue)
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n)
+ coproc <= 0;
+ else if(next_cycle == ISSUE && issue)
coproc <= dec.ctrl.coproc;
- initial
- coproc = 0;
-
endmodule
diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv
index f6bc517..0a70d5e 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/control/cycles.sv
@@ -3,6 +3,7 @@
module core_control_cycles
(
input logic clk,
+ rst_n,
mul,
ldst,
bubble,
@@ -61,10 +62,7 @@ module core_control_cycles
end
end
- always_ff @(posedge clk)
- cycle <= next_cycle;
-
- initial
- cycle = ISSUE;
+ always_ff @(posedge clk or negedge rst_n)
+ cycle <= !rst_n ? ISSUE : next_cycle;
endmodule
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv
index 0d87b02..fc936dc 100644
--- a/rtl/core/control/data.sv
+++ b/rtl/core/control/data.sv
@@ -3,6 +3,7 @@
module core_control_data
(
input logic clk,
+ rst_n,
input insn_decode dec,
input word rd_value_a,
@@ -62,8 +63,16 @@ module core_control_data
endcase
end
- always_ff @(posedge clk)
- unique case(next_cycle)
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ alu <= {$bits(alu){1'b0}};
+ c_in <= 0;
+ shifter <= {$bits(shifter){1'b0}};
+ data_imm <= {$bits(data_imm){1'b0}};
+ data_shift_imm <= {$bits(data_shift_imm){1'b0}};
+ data_snd_is_imm <= 0;
+ data_snd_shift_by_reg <= 0;
+ end else unique case(next_cycle)
ISSUE: begin
alu <= dec.data.op;
c_in <= flags.c;
@@ -100,14 +109,4 @@ module core_control_data
end
endcase
- initial begin
- alu = {$bits(alu){1'b0}};
- c_in = 0;
- shifter = {$bits(shifter){1'b0}};
- data_imm = {$bits(data_imm){1'b0}};
- data_shift_imm = {$bits(data_shift_imm){1'b0}};
- data_snd_is_imm = 0;
- data_snd_shift_by_reg = 0;
- end
-
endmodule
diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv
index 9a64cd5..c4f3772 100644
--- a/rtl/core/control/exception.sv
+++ b/rtl/core/control/exception.sv
@@ -3,6 +3,7 @@
module core_control_exception
(
input logic clk,
+ rst_n,
input logic undefined,
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index e3644c4..e3eb338 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -3,6 +3,7 @@
module core_control_issue
(
input logic clk,
+ rst_n,
input insn_decode dec,
input ptr insn_pc,
@@ -24,8 +25,12 @@ module core_control_issue
assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble;
assign next_pc_visible = insn_pc + 2;
- always_ff @(posedge clk)
- if(next_cycle == ISSUE) begin
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ pc <= 0;
+ undefined <= 0;
+ pc_visible <= 2;
+ end else if(next_cycle == ISSUE) begin
undefined <= dec.ctrl.undefined;
`ifdef VERILATOR
@@ -37,10 +42,4 @@ module core_control_issue
pc_visible <= next_pc_visible;
end
- initial begin
- pc = 0;
- pc_visible = 2;
- undefined = 0;
- end
-
endmodule
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index 2a295c8..baf0054 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -3,6 +3,7 @@
module core_control_ldst
(
input logic clk,
+ rst_n,
input insn_decode dec,
input logic issue,
@@ -43,8 +44,19 @@ module core_control_ldst
.pop_lower(popped_lower)
);
- always_ff @(posedge clk)
- unique case(next_cycle)
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ ldst <= 0;
+ ldst_pre <= 0;
+ ldst_writeback <= 0;
+ ldst_increment <= 0;
+
+ mem_addr <= {$bits(mem_addr){1'b0}};
+ mem_write <= 0;
+ mem_start <= 0;
+ mem_regs <= {$bits(mem_regs){1'b0}};
+ mem_offset <= 0;
+ end else unique case(next_cycle)
ISSUE: begin
// TODO: dec.ldst.unprivileged/user_regs
// TODO: byte/halfword sizes
@@ -74,17 +86,4 @@ module core_control_ldst
end
endcase
- initial begin
- ldst = 0;
- ldst_pre = 0;
- ldst_writeback = 0;
- ldst_increment = 0;
-
- mem_addr = {$bits(mem_addr){1'b0}};
- mem_write = 0;
- mem_start = 0;
- mem_regs = {$bits(mem_regs){1'b0}};
- mem_offset = 0;
- end
-
endmodule
diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv
index 8f7cd91..9e66053 100644
--- a/rtl/core/control/mul.sv
+++ b/rtl/core/control/mul.sv
@@ -3,6 +3,7 @@
module core_control_mul
(
input logic clk,
+ rst_n,
input insn_decode dec,
input logic mul_ready,
@@ -31,42 +32,41 @@ module core_control_mul
assign {mul_c_hi, mul_c_lo} = {rd_value_a, rd_value_b};
assign {mul_a, mul_b} = mul_add ? {hold_a, hold_b} : {rd_value_a, rd_value_b};
- always_ff @(posedge clk) begin
- mul_start <= 0;
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ mul <= 0;
+ mul_add <= 0;
+ mul_long <= 0;
+ mul_start <= 0;
+ mul_signed <= 0;
+ mul_r_add_hi <= {$bits(mul_r_add_hi){1'b0}};
+ mul_r_add_lo <= {$bits(mul_r_add_lo){1'b0}};
- unique case(next_cycle)
- ISSUE: begin
- mul <= issue && dec.ctrl.mul;
- mul_add <= dec.mul.add;
- mul_long <= dec.mul.long_mul;
- mul_signed <= dec.mul.signed_mul;
- mul_r_add_hi <= dec.mul.r_add_hi;
- mul_r_add_lo <= dec.mul.r_add_lo;
- end
+ hold_a <= 0;
+ hold_b <= 0;
+ end else begin
+ mul_start <= 0;
- MUL:
- mul_start <= cycle != MUL;
+ unique case(next_cycle)
+ ISSUE: begin
+ mul <= issue && dec.ctrl.mul;
+ mul_add <= dec.mul.add;
+ mul_long <= dec.mul.long_mul;
+ mul_signed <= dec.mul.signed_mul;
+ mul_r_add_hi <= dec.mul.r_add_hi;
+ mul_r_add_lo <= dec.mul.r_add_lo;
+ end
- MUL_ACC_LD: begin
- hold_a <= rd_value_a;
- hold_b <= rd_value_b;
- end
- endcase
- end
+ MUL:
+ mul_start <= cycle != MUL;
- //TODO: mul update_flags
-
- initial begin
- mul = 0;
- mul_add = 0;
- mul_long = 0;
- mul_start = 0;
- mul_signed = 0;
- mul_r_add_hi = {$bits(mul_r_add_hi){1'b0}};
- mul_r_add_lo = {$bits(mul_r_add_lo){1'b0}};
+ MUL_ACC_LD: begin
+ hold_a <= rd_value_a;
+ hold_b <= rd_value_b;
+ end
+ endcase
+ end
- hold_a = 0;
- hold_b = 0;
- end
+ //TODO: mul update_flags
endmodule
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index 09fb144..80a437f 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -3,6 +3,7 @@
module core_control_select
(
input logic clk,
+ rst_n,
input insn_decode dec,
@@ -46,18 +47,17 @@ module core_control_select
endcase
end
- always_ff @(posedge clk) begin
- last_ra <= ra;
- last_rb <= rb;
-
- if(next_cycle == ISSUE)
- r_shift <= dec.snd.r_shift;
- end
-
- initial begin
- last_ra = {$bits(ra){1'b0}};
- last_rb = {$bits(rb){1'b0}};
- r_shift = {$bits(r_shift){1'b0}};
- end
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ last_ra <= {$bits(ra){1'b0}};
+ last_rb <= {$bits(rb){1'b0}};
+ r_shift <= {$bits(r_shift){1'b0}};
+ end else begin
+ last_ra <= ra;
+ last_rb <= rb;
+
+ if(next_cycle == ISSUE)
+ r_shift <= dec.snd.r_shift;
+ end
endmodule
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
index 223fecb..60dfbbe 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/control/stall.sv
@@ -3,6 +3,7 @@
module core_control_stall
(
input logic clk,
+ rst_n,
input insn_decode dec,
@@ -33,10 +34,7 @@ module core_control_stall
assign flags_dependency = dec.psr.update_flags || dec.ctrl.conditional;
assign updating_flags = final_update_flags || update_flags;
- always_ff @(posedge clk)
- bubble <= next_cycle == ISSUE && next_bubble;
-
- initial
- bubble = 0;
+ always_ff @(posedge clk or negedge rst_n)
+ bubble <= !rst_n ? 0 : next_cycle == ISSUE && next_bubble;
endmodule
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 73a8a4c..1fb3ced 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -3,6 +3,7 @@
module core_control_writeback
(
input logic clk,
+ rst_n,
input insn_decode dec,
input psr_flags alu_flags,
@@ -100,60 +101,59 @@ module core_control_writeback
endcase
end
- always_ff @(posedge clk) begin
- last_rd <= rd;
- wb_alu_flags <= alu_flags;
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ last_rd <= 0;
+ final_rd <= 0;
+ final_writeback <= 0;
- unique case(next_cycle)
- ISSUE:
- final_rd <= dec.data.rd;
+ update_flags <= 0;
+ final_update_flags <= 0;
- TRANSFER:
- if((cycle != TRANSFER || mem_ready) && pop_valid)
- final_rd <= popped;
+ wb_alu_flags <= {$bits(wb_alu_flags){1'b0}};
+ end else begin
+ last_rd <= rd;
+ wb_alu_flags <= alu_flags;
- BASE_WRITEBACK:
- final_rd <= ra;
+ unique case(next_cycle)
+ ISSUE:
+ final_rd <= dec.data.rd;
- EXCEPTION:
- final_rd <= `R14;
- endcase
+ TRANSFER:
+ if((cycle != TRANSFER || mem_ready) && pop_valid)
+ final_rd <= popped;
- unique case(next_cycle)
- ISSUE:
- final_writeback <= issue && dec.ctrl.writeback;
+ BASE_WRITEBACK:
+ final_rd <= ra;
- EXCEPTION:
- final_writeback <= 1;
- endcase
+ EXCEPTION:
+ final_rd <= `R14;
+ endcase
- update_flags <= 0;
- unique case(next_cycle)
- ISSUE:
- update_flags <= final_update_flags;
+ unique case(next_cycle)
+ ISSUE:
+ final_writeback <= issue && dec.ctrl.writeback;
- EXCEPTION:
- final_update_flags <= 0;
- endcase
-
- unique case(next_cycle)
- ISSUE:
- final_update_flags <= issue && dec.psr.update_flags;
+ EXCEPTION:
+ final_writeback <= 1;
+ endcase
- EXCEPTION:
- final_update_flags <= 0;
- endcase
- end
+ update_flags <= 0;
+ unique case(next_cycle)
+ ISSUE:
+ update_flags <= final_update_flags;
- initial begin
- last_rd = 0;
- final_rd = 0;
- final_writeback = 0;
+ EXCEPTION:
+ final_update_flags <= 0;
+ endcase
- update_flags = 0;
- final_update_flags = 0;
+ unique case(next_cycle)
+ ISSUE:
+ final_update_flags <= issue && dec.psr.update_flags;
- wb_alu_flags = {$bits(wb_alu_flags){1'b0}};
- end
+ EXCEPTION:
+ final_update_flags <= 0;
+ endcase
+ end
endmodule
diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/cp15/cp15.sv
index 3855e13..907576a 100644
--- a/rtl/core/cp15/cp15.sv
+++ b/rtl/core/cp15/cp15.sv
@@ -4,6 +4,7 @@
module core_cp15
(
input logic clk,
+ rst_n,
transfer,
input coproc_decode dec,
input word write,
diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv
index bb52443..dc97909 100644
--- a/rtl/core/fetch/fetch.sv
+++ b/rtl/core/fetch/fetch.sv
@@ -4,6 +4,7 @@ module core_fetch
#(parameter PREFETCH_ORDER=2)
(
input logic clk,
+ rst_n,
stall,
branch,
fetched,
@@ -49,14 +50,13 @@ module core_fetch
addr = hold_addr;
end
- always_ff @(posedge clk) begin
- discard <= discard ? !fetched : flush && fetch;
- hold_addr <= addr;
- end
-
- initial begin
- discard = 0;
- hold_addr = 0;
- end
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ discard <= 0;
+ hold_addr <= 0;
+ end else begin
+ discard <= discard ? !fetched : flush && fetch;
+ hold_addr <= addr;
+ end
endmodule
diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/fetch/prefetch.sv
index 4025339..2f0a866 100644
--- a/rtl/core/fetch/prefetch.sv
+++ b/rtl/core/fetch/prefetch.sv
@@ -4,6 +4,7 @@ module core_prefetch
#(parameter ORDER=2)
(
input logic clk,
+ rst_n,
stall,
flush,
fetched,
@@ -25,43 +26,42 @@ module core_prefetch
assign next_pc = ~stall & |valid ? insn_pc + 1 : insn_pc;
assign fetch = !stall || ~&valid;
- always_ff @(posedge clk) begin
- insn_pc <= flush ? head : next_pc;
-
- if(flush)
- prefetch[SIZE - 1] <= `NOP;
- else if(fetched && valid == SIZE - 1 + {{(ORDER - 1){1'b0}}, !stall})
- prefetch[SIZE - 1] <= fetch_data;
- else if(!stall)
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ valid <= 0;
+ insn_pc <= 0;
prefetch[SIZE - 1] <= `NOP;
+ end else begin
+ insn_pc <= flush ? head : next_pc;
- if(flush)
- valid <= 0;
- else if(fetched & ((stall & ~&valid) | ~|valid))
- valid <= valid + 1;
- else if(~stall & ~fetched & |valid)
- valid <= valid - 1;
- end
+ if(flush)
+ prefetch[SIZE - 1] <= `NOP;
+ else if(fetched && valid == SIZE - 1 + {{(ORDER - 1){1'b0}}, !stall})
+ prefetch[SIZE - 1] <= fetch_data;
+ else if(!stall)
+ prefetch[SIZE - 1] <= `NOP;
+
+ if(flush)
+ valid <= 0;
+ else if(fetched & ((stall & ~&valid) | ~|valid))
+ valid <= valid + 1;
+ else if(~stall & ~fetched & |valid)
+ valid <= valid - 1;
+ end
genvar i;
generate
for(i = 0; i < SIZE - 1; ++i) begin: prefetch_slots
- always_ff @(posedge clk)
- if(flush)
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n)
+ prefetch[i] <= `NOP;
+ else if(flush)
prefetch[i] <= `NOP;
else if(fetched & (~(|i | |valid) | (valid == i + {{(ORDER - 1){1'b0}}, ~stall})))
prefetch[i] <= fetch_data;
else if(~stall)
prefetch[i] <= prefetch[i + 1];
-
- initial prefetch[i] = `NOP;
end
endgenerate
- initial begin
- insn_pc = 0;
- valid = 0;
- prefetch[SIZE - 1] = `NOP;
- end
-
endmodule
diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv
index bf37cb0..185fb6b 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/mmu/mmu.sv
@@ -1,6 +1,7 @@
module core_mmu
(
input logic clk,
+ rst_n,
input logic bus_ready,
input word bus_data_rd,
@@ -80,35 +81,34 @@ module core_mmu
end
end
- always_ff @(posedge clk) begin
- master <= next_master;
- active <= bus_start || (active && !bus_ready);
-
- if(hold_free)
- unique case(next_master)
- INSN: begin
- hold_start <= data_start;
- hold_addr <= data_addr;
- hold_write <= data_write;
- hold_data_wr <= data_data_wr;
- end
-
- DATA: begin
- hold_start <= insn_start;
- hold_addr <= insn_addr;
- hold_write <= 0;
- end
- endcase
- end
-
- initial begin
- master = INSN;
- active = 0;
-
- hold_addr = 30'b0;
- hold_start = 0;
- hold_write = 0;
- hold_data_wr = 0;
- end
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ master <= INSN;
+ active <= 0;
+
+ hold_addr <= 30'b0;
+ hold_start <= 0;
+ hold_write <= 0;
+ hold_data_wr <= 0;
+ end else begin
+ master <= next_master;
+ active <= bus_start || (active && !bus_ready);
+
+ if(hold_free)
+ unique case(next_master)
+ INSN: begin
+ hold_start <= data_start;
+ hold_addr <= data_addr;
+ hold_write <= data_write;
+ hold_data_wr <= data_data_wr;
+ end
+
+ DATA: begin
+ hold_start <= insn_start;
+ hold_addr <= insn_addr;
+ hold_write <= 0;
+ end
+ endcase
+ end
endmodule
diff --git a/rtl/core/mul.sv b/rtl/core/mul.sv
index a801851..e189e45 100644
--- a/rtl/core/mul.sv
+++ b/rtl/core/mul.sv
@@ -4,6 +4,8 @@
module core_mul
(
input logic clk, // clock, ya que es una máquina de estados
+ rst_n,
+
input word a, // primer sumando
b, // segundo sumando
c_hi, // parte más significativa de c
@@ -31,7 +33,7 @@ module core_mul
dsp_mul ip
(
.clock0(clk),
- .aclr0(1), //TODO
+ .aclr0(rst_n),
.ena0(start || !ready),
.dataa_0(a),
.datab_0(b),
@@ -49,13 +51,12 @@ module core_mul
else
c = {{$bits(word){sig && c_lo[$bits(c_lo) - 1]}}, c_lo};
- always_ff @(posedge clk)
- if(wait_state > {$bits(wait_state){1'b0}})
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n)
+ wait_state <= 0;
+ else if(wait_state > {$bits(wait_state){1'b0}})
wait_state <= wait_state - 1;
else if(start)
wait_state <= 1;
- initial
- wait_state = 0;
-
endmodule
diff --git a/rtl/core/porch/porch.sv b/rtl/core/porch/porch.sv
index 6f5caf7..2eec438 100644
--- a/rtl/core/porch/porch.sv
+++ b/rtl/core/porch/porch.sv
@@ -3,6 +3,7 @@
module core_porch
(
input logic clk,
+ rst_n,
flush,
stall,
input psr_flags flags,
@@ -35,8 +36,12 @@ module core_porch
dec.ctrl.conditional = !flush && (dec.ctrl.conditional || conditional);
end
- always @(posedge clk)
- if(!stall) begin
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ insn <= `NOP;
+ insn_pc <= 0;
+ hold_dec <= nop;
+ end else if(!stall) begin
insn <= fetch_insn;
hold_dec <= fetch_dec;
@@ -44,10 +49,4 @@ module core_porch
insn_pc <= fetch_insn_pc;
end
- initial begin
- insn = `NOP;
- insn_pc = 0;
- hold_dec = nop;
- end
-
endmodule
diff --git a/rtl/core/psr.sv b/rtl/core/psr.sv
index 0bccfb7..67c3455 100644
--- a/rtl/core/psr.sv
+++ b/rtl/core/psr.sv
@@ -3,6 +3,7 @@
module core_psr
(
input logic clk,
+ rst_n,
write,
saved,
update_flags,
@@ -119,41 +120,40 @@ module core_psr
end
end
- always_ff @(posedge clk) begin
- wr_flags <= next_flags;
- pending_update <= !write && update_flags;
-
- if(!write) begin
- if(pending_update)
- cpsr.flags <= wr_flags;
- end else if(!saved)
- cpsr <= wr_clean;
- else
- unique case(mode)
- `MODE_SVC: spsr_svc <= wr_clean;
- `MODE_ABT: spsr_abt <= wr_clean;
- `MODE_UND: spsr_und <= wr_clean;
- `MODE_IRQ: spsr_irq <= wr_clean;
- `MODE_FIQ: spsr_fiq <= wr_clean;
- default: ;
- endcase
- end
-
- initial begin
- wr_flags = 4'b0000;
- pending_update = 0;
-
- cpsr.mode = `MODE_SVC;
- cpsr.flags = 4'b0000;
- cpsr.mask.a = 1;
- cpsr.mask.i = 1;
- cpsr.mask.f = 1;
-
- spsr_svc = {$bits(spsr_svc){1'b0}};
- spsr_abt = {$bits(spsr_svc){1'b0}};
- spsr_und = {$bits(spsr_svc){1'b0}};
- spsr_irq = {$bits(spsr_svc){1'b0}};
- spsr_fiq = {$bits(spsr_svc){1'b0}};
- end
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ wr_flags <= 4'b0000;
+ pending_update <= 0;
+
+ cpsr.mode <= `MODE_SVC;
+ cpsr.flags <= 4'b0000;
+ cpsr.mask.a <= 1;
+ cpsr.mask.i <= 1;
+ cpsr.mask.f <= 1;
+
+ spsr_svc <= {$bits(spsr_svc){1'b0}};
+ spsr_abt <= {$bits(spsr_svc){1'b0}};
+ spsr_und <= {$bits(spsr_svc){1'b0}};
+ spsr_irq <= {$bits(spsr_svc){1'b0}};
+ spsr_fiq <= {$bits(spsr_svc){1'b0}};
+ end else begin
+ wr_flags <= next_flags;
+ pending_update <= !write && update_flags;
+
+ if(!write) begin
+ if(pending_update)
+ cpsr.flags <= wr_flags;
+ end else if(!saved)
+ cpsr <= wr_clean;
+ else
+ unique case(mode)
+ `MODE_SVC: spsr_svc <= wr_clean;
+ `MODE_ABT: spsr_abt <= wr_clean;
+ `MODE_UND: spsr_und <= wr_clean;
+ `MODE_IRQ: spsr_irq <= wr_clean;
+ `MODE_FIQ: spsr_fiq <= wr_clean;
+ default: ;
+ endcase
+ end
endmodule
diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv
index 38c3301..d9ac251 100644
--- a/rtl/core/regs/file.sv
+++ b/rtl/core/regs/file.sv
@@ -3,6 +3,8 @@
module core_reg_file
(
input logic clk,
+ rst_n,
+
input psr_mode rd_mode,
input reg_num rd_r,
input reg_index wr_index,
@@ -31,19 +33,18 @@ module core_reg_file
assign rd_value = hold_rd_pc ? pc_word : forward ? wr_current : rd_actual;
- always_ff @(posedge clk) begin
- forward <= wr_enable && rd_index == wr_index;
- hold_rd_pc <= rd_pc;
-
- if(wr_enable_file)
- file[wr_index] <= wr_value;
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ forward <= 0;
+ hold_rd_pc <= 0;
+ end else begin
+ forward <= wr_enable && rd_index == wr_index;
+ hold_rd_pc <= rd_pc;
- rd_actual <= file[rd_index];
- end
+ if(wr_enable_file)
+ file[wr_index] <= wr_value;
- initial begin
- forward = 0;
- hold_rd_pc = 0;
- end
+ rd_actual <= file[rd_index];
+ end
endmodule
diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv
index 9cf7033..f9cecad 100644
--- a/rtl/core/regs/regs.sv
+++ b/rtl/core/regs/regs.sv
@@ -3,6 +3,8 @@
module core_regs
(
input logic clk,
+ rst_n,
+
input reg_num rd_r_a,
rd_r_b,
wr_r,
@@ -53,16 +55,15 @@ module core_regs
.index(wr_index)
);
- always_ff @(posedge clk) begin
- if(wr_enable)
- wr_current <= wr_value;
-
- branch <= wr_enable && wr_pc;
- end
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ branch <= 0;
+ wr_current <= 0;
+ end else begin
+ if(wr_enable)
+ wr_current <= wr_value;
- initial begin
- branch = 0;
- wr_current = 0;
- end
+ branch <= wr_enable && wr_pc;
+ end
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 13:57:42 +0000