diff options
Diffstat (limited to 'rtl/core')
| -rw-r--r-- | rtl/core/arm810.sv | 4 | ||||
| -rw-r--r-- | rtl/core/control/control.sv | 20 | ||||
| -rw-r--r-- | rtl/core/control/cycles.sv | 14 | ||||
| -rw-r--r-- | rtl/core/control/stall.sv | 2 | ||||
| -rw-r--r-- | rtl/core/uarch.sv | 3 |
5 files changed, 34 insertions, 9 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 517c8de..6028e91 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -122,6 +122,10 @@ module arm810 .c(c_shifter) ); + //TODO + logic mul, mul_add, mul_long, mul_signed, mul_ready; + assign mul_ready = 1; + ptr data_addr; logic data_start, data_write, data_ready, insn_ready; word data_data_rd, data_data_wr, insn_data_rd; diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 929d53a..4169986 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -8,6 +8,7 @@ module core_control input data_decode dec_data, input snd_decode dec_snd, input ldst_decode dec_ldst, + input mul_decode dec_mul, input ptr fetch_insn_pc, input psr_flags flags, alu_flags, @@ -18,6 +19,7 @@ module core_control input logic c_shifter, mem_ready, input word mem_data_rd, + input logic mul_ready, `ifdef VERILATOR input word insn, @@ -44,13 +46,16 @@ module core_control output ptr mem_addr, output word mem_data_wr, output logic mem_start, - mem_write + mem_write, + mul, + mul_add, + mul_long, + mul_signed ); - logic final_writeback, final_update_flags, - ldst, ldst_pre, ldst_increment, ldst_writeback, pop_valid, - data_snd_is_imm, data_snd_shift_by_reg, trivial_shift, - undefined, exception, high_vectors; + logic final_writeback, final_update_flags, ldst, ldst_pre, ldst_increment, + ldst_writeback, pop_valid, data_snd_is_imm, data_snd_shift_by_reg, + trivial_shift, undefined, exception, high_vectors; logic[2:0] vector_offset; logic[5:0] data_shift_imm; @@ -146,6 +151,11 @@ module core_control ldst_increment <= dec_ldst.increment; ldst_writeback <= dec_ldst.writeback; + mul <= dec.mul; + mul_add <= dec_mul.add; + mul_long <= dec_mul.long_mul; + mul_signed <= dec_mul.signed_mul; + mem_regs <= dec_ldst.regs; mem_write <= !dec_ldst.load; diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv index f804e93..e9bc2da 100644 --- a/rtl/core/control/cycles.sv +++ b/rtl/core/control/cycles.sv @@ -3,10 +3,12 @@ module core_control_cycles ( input logic clk, + mul, ldst, bubble, exception, mem_ready, + mul_ready, pop_valid, trivial_shift, ldst_writeback, @@ -38,13 +40,21 @@ module core_control_cycles else if(ldst_writeback) next_cycle = BASE_WRITEBACK; + MUL: + if(!mul_ready) + next_cycle = MUL; + default: ; endcase if(bubble) next_cycle = ISSUE; - else if(next_cycle == ISSUE && ldst) - next_cycle = TRANSFER; + else if(next_cycle == ISSUE) begin + if(ldst) + next_cycle = TRANSFER; + else if(mul) + next_cycle = MUL; + end end always_ff @(posedge clk) diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv index 4dc56e4..5ac1c7a 100644 --- a/rtl/core/control/stall.sv +++ b/rtl/core/control/stall.sv @@ -36,7 +36,7 @@ module core_control_stall assign updating_flags = final_update_flags || update_flags; always_ff @(posedge clk) - bubble <= next_cycle == ISSUE ? next_bubble : 0; + bubble <= next_cycle == ISSUE && next_bubble; initial bubble = 0; diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv index 3b9351d..3e42688 100644 --- a/rtl/core/uarch.sv +++ b/rtl/core/uarch.sv @@ -141,7 +141,8 @@ typedef enum WITH_SHIFT, TRANSFER, BASE_WRITEBACK, - EXCEPTION + EXCEPTION, + MUL } ctrl_cycle; typedef struct packed |