diff options
Diffstat (limited to '')
| -rw-r--r-- | rtl/core/arm810.sv | 4 | ||||
| -rw-r--r-- | rtl/core/control/control.sv | 4 | ||||
| -rw-r--r-- | rtl/core/control/cycles.sv | 3 | ||||
| -rw-r--r-- | rtl/core/control/issue.sv | 3 | ||||
| -rw-r--r-- | rtl/core/control/stall.sv | 7 |
5 files changed, 16 insertions, 5 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 9b36a41..2600e51 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -5,13 +5,15 @@ module arm810 input logic clk, rst_n, irq, + halt, output ptr bus_addr, output logic bus_start, bus_write, input logic bus_ready, input word bus_data_rd, - output word bus_data_wr + output word bus_data_wr, + output logic halted ); ptr fetch_insn_pc, fetch_head, insn_addr; diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 45e8e10..d204b96 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -4,6 +4,7 @@ module core_control ( input logic clk, rst_n, + halt, input insn_decode dec, input ptr insn_pc, @@ -24,7 +25,8 @@ module core_control input word insn, `endif - output logic stall, + output logic halted, + stall, branch, writeback, update_flags, diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv index 0a70d5e..0c5d94c 100644 --- a/rtl/core/control/cycles.sv +++ b/rtl/core/control/cycles.sv @@ -4,6 +4,7 @@ module core_control_cycles ( input logic clk, rst_n, + halt, mul, ldst, bubble, @@ -28,6 +29,8 @@ module core_control_cycles ISSUE: if(exception) next_cycle = EXCEPTION; + else if(halt) + next_cycle = ISSUE; else if(mul) next_cycle = mul_add ? MUL_ACC_LD : MUL; else if(data_snd_shift_by_reg) diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv index e3eb338..b2ee6e5 100644 --- a/rtl/core/control/issue.sv +++ b/rtl/core/control/issue.sv @@ -4,6 +4,7 @@ module core_control_issue ( input logic clk, rst_n, + halt, input insn_decode dec, input ptr insn_pc, @@ -22,7 +23,7 @@ module core_control_issue next_pc_visible ); - assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble; + assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble && !halt; assign next_pc_visible = insn_pc + 2; always_ff @(posedge clk or negedge rst_n) diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv index 6d2b4e2..c2a6ddd 100644 --- a/rtl/core/control/stall.sv +++ b/rtl/core/control/stall.sv @@ -4,6 +4,7 @@ module core_control_stall ( input logic clk, rst_n, + halt, input insn_decode dec, @@ -14,7 +15,8 @@ module core_control_stall writeback, input reg_num final_rd, - output logic stall, + output logic halted, + stall, bubble, next_bubble ); @@ -22,7 +24,8 @@ module core_control_stall logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard, flags_hazard, flags_dependency, updating_flags; - assign stall = next_cycle != ISSUE || next_bubble; + assign stall = next_cycle != ISSUE || next_bubble || halt; + assign halted = halt && !next_bubble; assign next_bubble = pc_rd_hazard || pc_wr_hazard || flags_hazard; //FIXME: pc_rd_hazard no deberÃa definirse sin final_writeback? |