3 files changed, 4 insertions, 5 deletions

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index c43a832..c49600f 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -59,7 +59,7 @@ module arm810
 	word alu_a, alu_b, wr_value;
 	logic[7:0] shifter_shift;
 
-	core_cycles cycles
+	core_control control
 	(
 		.branch(explicit_branch),
 		.alu(alu_ctrl),
diff --git a/rtl/core/cycles.sv b/rtl/core/control/control.sv
index ad35762..398c8c7 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/control/control.sv
@@ -1,6 +1,6 @@
 `include "core/uarch.sv"
 
-module core_cycles
+module core_control
 (
 	input  logic           clk,
 	                       dec_execute,
@@ -76,7 +76,7 @@ module core_cycles
 		   ((dec_update_flags || dec_conditional) && (final_update_flags || update_flags))
 		|| (final_writeback && (final_rd == dec_data.rn || final_rd == dec_snd.r));
 
-	core_cycles_ldst_pop ldst_pop
+	core_control_ldst_pop ldst_pop
 	(
 		.regs(mem_regs),
 		.valid(pop_valid),
@@ -171,7 +171,6 @@ module core_cycles
 					data_imm <= dec_snd.imm;
 					data_shift_imm <= dec_snd.shift_imm;
 
-					shifter.shl <= dec_snd.shl;
 					shifter.shr <= dec_snd.shr;
 					shifter.ror <= dec_snd.ror;
 					shifter.put_carry <= dec_snd.put_carry;
diff --git a/rtl/core/cycles/ldst/pop.sv b/rtl/core/control/ldst/pop.sv
index a4078d1..64dc04d 100644
--- a/rtl/core/cycles/ldst/pop.sv
+++ b/rtl/core/control/ldst/pop.sv
@@ -1,6 +1,6 @@
 `include "core/uarch.sv"
 
-module core_cycles_ldst_pop
+module core_control_ldst_pop
 (
 	input  reg_list regs,