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-rw-r--r--rtl/core/regs/file.sv25
1 files changed, 13 insertions, 12 deletions
diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv
index 38c3301..d9ac251 100644
--- a/rtl/core/regs/file.sv
+++ b/rtl/core/regs/file.sv
@@ -3,6 +3,8 @@
module core_reg_file
(
input logic clk,
+ rst_n,
+
input psr_mode rd_mode,
input reg_num rd_r,
input reg_index wr_index,
@@ -31,19 +33,18 @@ module core_reg_file
assign rd_value = hold_rd_pc ? pc_word : forward ? wr_current : rd_actual;
- always_ff @(posedge clk) begin
- forward <= wr_enable && rd_index == wr_index;
- hold_rd_pc <= rd_pc;
-
- if(wr_enable_file)
- file[wr_index] <= wr_value;
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ forward <= 0;
+ hold_rd_pc <= 0;
+ end else begin
+ forward <= wr_enable && rd_index == wr_index;
+ hold_rd_pc <= rd_pc;
- rd_actual <= file[rd_index];
- end
+ if(wr_enable_file)
+ file[wr_index] <= wr_value;
- initial begin
- forward = 0;
- hold_rd_pc = 0;
- end
+ rd_actual <= file[rd_index];
+ end
endmodule