4 files changed, 34 insertions, 34 deletions

diff --git a/rtl/core/decode/data.sv b/rtl/core/decode/data.sv
index 103fb14..1bd7ef9 100644
--- a/rtl/core/decode/data.sv
+++ b/rtl/core/decode/data.sv
@@ -10,16 +10,18 @@ module core_decode_data
 	                   snd_shift_by_reg_if_reg,
 	                   writeback,
 	                   update_flags,
-	                   restore_spsr,
-	                   uses_rn
+	                   restore_spsr
 );
 
 	alu_op op;
 	reg_num rn, rd;
+	logic uses_rn;
 
 	assign decode.op = op;
 	assign decode.rn = rn;
 	assign decode.rd = rd;
+	assign decode.uses_rn = uses_rn;
+
 	assign rn = insn `FIELD_DATA_RN;
 	assign rd = insn `FIELD_DATA_RD;
 	assign op = insn `FIELD_DATA_OPCODE;
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index 9367e6d..2740b70 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -3,22 +3,25 @@
 
 module core_decode
 (
-	input  word        insn,
-	input  psr_flags   flags,
-
-	output logic       execute,
-	                   conditional,
-	                   undefined,
-	                   writeback,
-	                   update_flags,
-	                   uses_rn,
-	                   branch,
-	output ptr         branch_offset,
-	output snd_decode  snd_ctrl,
-	output data_decode data_ctrl,
-	output ldst_decode ldst_ctrl
+	input  word            insn,
+	input  psr_flags       flags,
+
+	output datapath_decode ctrl,
+	output branch_decode   branch_ctrl,
+	output snd_decode      snd_ctrl,
+	output data_decode     data_ctrl,
+	output ldst_decode     ldst_ctrl
 );
 
+	logic execute, undefined, conditional, writeback, update_flags, branch;
+
+	assign ctrl.execute = execute;
+	assign ctrl.undefined = undefined;
+	assign ctrl.conditional = conditional;
+	assign ctrl.writeback = writeback;
+	assign ctrl.update_flags = update_flags;
+	assign branch_ctrl.branch = branch;
+
 	//TODO
 	logic restore_spsr;
 
@@ -50,13 +53,13 @@ module core_decode
 	core_decode_branch group_branch
 	(
 		.link(branch_link),
-		.offset(branch_offset),
+		.offset(branch_ctrl.offset),
 		.*
 	);
 
 	data_decode data;
 	logic data_writeback, data_update_flags, data_restore_spsr,
-	      data_is_imm, data_shift_by_reg_if_reg, data_uses_rn;
+	      data_is_imm, data_shift_by_reg_if_reg;
 
 	core_decode_data group_data
 	(
@@ -66,7 +69,6 @@ module core_decode
 		.restore_spsr(data_restore_spsr),
 		.snd_is_imm(data_is_imm),
 		.snd_shift_by_reg_if_reg(data_shift_by_reg_if_reg),
-		.uses_rn(data_uses_rn),
 		.*
 	);
 
@@ -117,11 +119,11 @@ module core_decode
 		branch = 0;
 		writeback = 0;
 		update_flags = 0;
-		uses_rn = 1;
 		execute = cond_execute;
 		undefined = cond_undefined;
 
 		data_ctrl = {($bits(data_ctrl)){1'bx}};
+		data_ctrl.uses_rn = 1;
 
 		snd_ctrl = {$bits(snd_ctrl){1'bx}};
 		snd_ctrl.shr = 0;
@@ -152,7 +154,6 @@ module core_decode
 			end
 
 			`GROUP_ALU: begin
-				uses_rn = data_uses_rn;
 				snd_is_imm = data_is_imm;
 				snd_ror_if_imm = 1;
 				snd_shift_by_reg_if_reg = data_shift_by_reg_if_reg;
@@ -227,7 +228,6 @@ module core_decode
 			execute = 0;
 
 			branch = 1'bx;
-			uses_rn = 1'bx;
 			writeback = 1'bx;
 			conditional = 1'bx;
 			update_flags = 1'bx;
diff --git a/rtl/core/decode/isa.sv b/rtl/core/decode/isa.sv
index baaf371..98d338e 100644
--- a/rtl/core/decode/isa.sv
+++ b/rtl/core/decode/isa.sv
@@ -66,7 +66,9 @@
 `define INSN_BIC 28'b00_?_1110_?_????_????_????????????
 `define INSN_MVN 28'b00_?_1111_?_0000_????_????????????
 
-`define GROUP_ALU 28'b00_?_????_?_????_????_????????????
+`define GROUP_ALU \
+	`INSN_AND, `INSN_EOR, `INSN_SUB, `INSN_RSB, `INSN_ADD, `INSN_ADC, `INSN_SBC, `INSN_RSC, \
+	`INSN_TST, `INSN_TEQ, `INSN_CMP, `INSN_CMN, `INSN_ORR, `INSN_MOV, `INSN_BIC, `INSN_MVN
 
 `define FIELD_DATA_IMM      [25]
 `define FIELD_DATA_OPCODE   [24:21]
diff --git a/rtl/core/decode/snd.sv b/rtl/core/decode/snd.sv
index 78c5424..264982e 100644
--- a/rtl/core/decode/snd.sv
+++ b/rtl/core/decode/snd.sv
@@ -41,23 +41,21 @@ module core_decode_snd
 		ror = is_imm;
 		shr = ~is_imm;
 		put_carry = 0;
-		sign_extend = 1'bx;
+		sign_extend = 0;
 
-		if(is_imm && !ror_if_imm)
-			shift_imm = 6'b0;
-		else if(is_imm && !ror_if_imm)
-			shift_imm = {1'b0, insn `FIELD_SND_ROR8, 1'b0};
+		if(is_imm)
+			shift_imm = ror_if_imm ? {1'b0, insn `FIELD_SND_ROR8, 1'b0} : 6'b0;
 		else begin
 			shift_imm = {1'b0, insn `FIELD_SND_SHIFTIMM};
 
 			case(shift_op)
 				`SHIFT_LSL: shr = 0;
-				`SHIFT_LSR: sign_extend = 0;
+				`SHIFT_LSR: ;
 				`SHIFT_ASR: sign_extend = 1;
-				`SHIFT_ROR: ;
+				`SHIFT_ROR: ror = 1;
 			endcase
 
-			if(~shift_by_reg & (shift_imm == 0))
+			if(!shift_by_reg && shift_imm == 0)
 				case(shift_op)
 					`SHIFT_LSL: ;
 
@@ -66,13 +64,11 @@ module core_decode_snd
 
 					`SHIFT_ROR: begin
 						// RRX
+						ror = 0;
 						shift_imm = 6'd1;
 						put_carry = 1;
-						sign_extend = 0;
 					end
 				endcase
-			else if(shift_op == `SHIFT_ROR)
-				ror = 1;
 		end
 	end