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-rw-r--r--rtl/core/decode/branch_dec.sv18
-rw-r--r--rtl/core/decode/coproc_dec.sv24
-rw-r--r--rtl/core/decode/data_dec.sv65
-rw-r--r--rtl/core/decode/decode.sv195
-rw-r--r--rtl/core/decode/isa.sv227
-rw-r--r--rtl/core/decode/ldst/addr.sv15
-rw-r--r--rtl/core/decode/ldst/exclusive.sv27
-rw-r--r--rtl/core/decode/ldst/misc.sv36
-rw-r--r--rtl/core/decode/ldst/multiple.sv34
-rw-r--r--rtl/core/decode/ldst/single.sv31
-rw-r--r--rtl/core/decode/mrs.sv15
-rw-r--r--rtl/core/decode/msr.sv17
-rw-r--r--rtl/core/decode/mul_dec.sv33
-rw-r--r--rtl/core/decode/mux.sv295
-rw-r--r--rtl/core/decode/snd.sv75
15 files changed, 0 insertions, 1107 deletions
diff --git a/rtl/core/decode/branch_dec.sv b/rtl/core/decode/branch_dec.sv
deleted file mode 100644
index 1dbc1ad..0000000
--- a/rtl/core/decode/branch_dec.sv
+++ /dev/null
@@ -1,18 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_branch
-(
- input word insn,
-
- output logic link,
- output ptr offset
-);
-
- logic[23:0] immediate;
- assign immediate = insn `FIELD_B_OFFSET;
-
- assign link = insn `FIELD_B_L;
- assign offset = {{6{immediate[23]}}, immediate};
-
-endmodule
diff --git a/rtl/core/decode/coproc_dec.sv b/rtl/core/decode/coproc_dec.sv
deleted file mode 100644
index 153cadf..0000000
--- a/rtl/core/decode/coproc_dec.sv
+++ /dev/null
@@ -1,24 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_coproc
-(
- input word insn,
-
- output coproc_decode decode,
- output reg_num rd,
- output logic writeback,
- update_flags
-);
-
- assign rd = insn `FIELD_CP_RD;
- assign writeback = decode.load && rd != `R15;
- assign update_flags = decode.load && rd == `R15;
-
- assign decode.crn = insn `FIELD_CP_CRN;
- assign decode.crm = insn `FIELD_CP_CRM;
- assign decode.op1 = insn `FIELD_CP_OPCODE;
- assign decode.op2 = insn `FIELD_CP_OPCODE2;
- assign decode.load = insn `FIELD_CP_LOAD;
-
-endmodule
diff --git a/rtl/core/decode/data_dec.sv b/rtl/core/decode/data_dec.sv
deleted file mode 100644
index f744972..0000000
--- a/rtl/core/decode/data_dec.sv
+++ /dev/null
@@ -1,65 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_data
-(
- input word insn,
-
- output data_decode decode,
- output logic snd_is_imm,
- snd_shift_by_reg_if_reg,
- writeback,
- conditional,
- update_flags,
- restore_spsr
-);
-
- alu_op op;
- reg_num rn, rd;
- logic uses_rn;
-
- assign decode.op = op;
- assign decode.rn = rn;
- assign decode.rd = rd;
- assign decode.uses_rn = uses_rn;
-
- assign rn = insn `FIELD_DATA_RN;
- assign rd = insn `FIELD_DATA_RD;
- assign op = insn `FIELD_DATA_OPCODE;
-
- assign snd_is_imm = insn `FIELD_DATA_IMM;
- assign snd_shift_by_reg_if_reg = insn `FIELD_DATA_REGSHIFT;
-
- always_comb begin
- unique case(op)
- `ALU_ADC, `ALU_SBC, `ALU_RSC:
- conditional = 1;
-
- default:
- conditional = 0;
- endcase
-
- unique case(op)
- `ALU_CMP, `ALU_CMN, `ALU_TST, `ALU_TEQ:
- writeback = 0;
-
- default:
- writeback = 1;
- endcase
-
- unique case(op)
- `ALU_MOV, `ALU_MVN:
- uses_rn = 0;
-
- default:
- uses_rn = 1;
- endcase
-
- update_flags = insn `FIELD_DATA_S;
- restore_spsr = (rd == `R15) & update_flags;
-
- if(restore_spsr)
- update_flags = 0;
- end
-
-endmodule
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
deleted file mode 100644
index 219f975..0000000
--- a/rtl/core/decode/decode.sv
+++ /dev/null
@@ -1,195 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode
-(
- input word insn,
-
- output insn_decode dec
-);
-
- mul_decode dec_mul;
- psr_decode dec_psr;
- snd_decode dec_snd;
- ctrl_decode dec_ctrl;
- data_decode dec_data;
- ldst_decode dec_ldst;
- branch_decode dec_branch;
- coproc_decode dec_coproc;
-
- assign dec.mul = dec_mul;
- assign dec.psr = dec_psr;
- assign dec.snd = dec_snd;
- assign dec.ctrl = dec_ctrl;
- assign dec.data = dec_data;
- assign dec.ldst = dec_ldst;
- assign dec.branch = dec_branch;
- assign dec.coproc = dec_coproc;
-
- assign dec_ctrl.nop = 0;
- assign dec_ctrl.mul = mul;
- assign dec_ctrl.swi = swi;
- assign dec_ctrl.psr = psr;
- assign dec_ctrl.ldst = ldst;
- assign dec_ctrl.bkpt = bkpt;
- assign dec_ctrl.branch = branch;
- assign dec_ctrl.coproc = coproc;
- assign dec_ctrl.execute = execute;
- assign dec_ctrl.writeback = writeback;
- assign dec_ctrl.undefined = undefined;
- assign dec_ctrl.conditional = conditional;
-
- assign dec_psr.saved = psr_saved;
- assign dec_psr.write = psr_write;
- assign dec_psr.wr_flags = psr_wr_flags;
- assign dec_psr.wr_control = psr_wr_control;
- assign dec_psr.update_flags = update_flags;
- assign dec_psr.restore_spsr = restore_spsr;
-
- logic execute, undefined, conditional, writeback, update_flags,
- restore_spsr, branch, ldst, mul, swi, psr, coproc, bkpt,
- psr_saved, psr_write, psr_wr_flags, psr_wr_control;
-
- core_decode_mux mux
- (
- .*
- );
-
- logic snd_is_imm, snd_ror_if_imm, snd_shift_by_reg_if_reg, snd_undefined;
- snd_decode snd;
-
- core_decode_snd snd_operand
- (
- .decode(snd),
- .is_imm(snd_is_imm),
- .ror_if_imm(snd_ror_if_imm),
- .shift_by_reg_if_reg(snd_shift_by_reg_if_reg),
- .undefined(snd_undefined),
- .*
- );
-
- logic branch_link;
-
- core_decode_branch group_branch
- (
- .link(branch_link),
- .offset(dec_branch.offset),
- .*
- );
-
- data_decode data;
- logic data_writeback, data_update_flags, data_restore_spsr,
- data_is_imm, data_shift_by_reg_if_reg, data_conditional;
-
- core_decode_data group_data
- (
- .decode(data),
- .writeback(data_writeback),
- .conditional(data_conditional),
- .update_flags(data_update_flags),
- .restore_spsr(data_restore_spsr),
- .snd_is_imm(data_is_imm),
- .snd_shift_by_reg_if_reg(data_shift_by_reg_if_reg),
- .*
- );
-
- logic ldst_single_is_imm;
- ldst_decode ldst_single;
-
- core_decode_ldst_single group_ldst_single
- (
- .snd_is_imm(ldst_single_is_imm),
- .decode(ldst_single),
- .*
- );
-
- ldst_decode ldst_misc;
- logic ldst_misc_off_is_imm;
- reg_num ldst_misc_off_reg;
- logic[7:0] ldst_misc_off_imm;
-
- core_decode_ldst_misc group_ldst_misc
- (
- .decode(ldst_misc),
- .off_imm(ldst_misc_off_imm),
- .off_reg(ldst_misc_off_reg),
- .off_is_imm(ldst_misc_off_is_imm),
- .*
- );
-
- logic ldst_mult_restore_spsr;
- ldst_decode ldst_multiple;
-
- core_decode_ldst_multiple group_ldst_multiple
- (
- .decode(ldst_multiple),
- .restore_spsr(ldst_mult_restore_spsr),
- .*
- );
-
- reg_num ldst_ex_snd_r;
- ldst_decode ldst_exclusive;
-
- core_decode_ldst_exclusive group_ldst_ex
- (
- .snd_r(ldst_ex_snd_r),
- .decode(ldst_exclusive),
- .*
- );
-
- ldst_decode ldst_addr;
- data_decode data_ldst;
-
- core_decode_ldst_addr ldst2data
- (
- .ldst(ldst_addr),
- .alu(data_ldst)
- );
-
- logic mul_update_flags;
- reg_num mul_rd, mul_rs, mul_rm;
-
- core_decode_mul group_mul
- (
- .decode(dec_mul),
- .rd(mul_rd),
- .rs(mul_rs),
- .rm(mul_rm),
- .update_flags(mul_update_flags),
- .*
- );
-
- logic coproc_writeback, coproc_update_flags;
- reg_num coproc_rd;
-
- core_decode_coproc group_coproc
- (
- .rd(coproc_rd),
- .decode(dec_coproc),
- .writeback(coproc_writeback),
- .update_flags(coproc_update_flags),
- .*
- );
-
- logic mrs_spsr;
- reg_num mrs_rd;
-
- core_decode_mrs group_mrs
- (
- .rd(mrs_rd),
- .spsr(mrs_spsr),
- .*
- );
-
- logic msr_spsr, msr_is_imm;
- msr_mask msr_fields;
-
- core_decode_msr group_msr
- (
- .spsr(msr_spsr),
- .fields(msr_fields),
- .snd_is_imm(msr_is_imm),
- .*
- );
-
-endmodule
diff --git a/rtl/core/decode/isa.sv b/rtl/core/decode/isa.sv
deleted file mode 100644
index 6784eca..0000000
--- a/rtl/core/decode/isa.sv
+++ /dev/null
@@ -1,227 +0,0 @@
-`ifndef CORE_DECODE_ISA_SV
-`define CORE_DECODE_ISA_SV
-
-`define FIELD_COND [31:28]
-`define FIELD_OP [27:0]
-
-`define COND_EQ 4'b0000
-`define COND_NE 4'b0001
-`define COND_HS 4'b0010
-`define COND_LO 4'b0011
-`define COND_MI 4'b0100
-`define COND_PL 4'b0101
-`define COND_VS 4'b0110
-`define COND_VC 4'b0111
-`define COND_HI 4'b1000
-`define COND_LS 4'b1001
-`define COND_GE 4'b1010
-`define COND_LT 4'b1011
-`define COND_GT 4'b1100
-`define COND_LE 4'b1101
-`define COND_AL 4'b1110
-`define COND_UD 4'b1111 // Indefnido antes de ARMv5
-
-// Necesario para evitar caminos combinacionales largos en ALU
-`define FIELD_ALUOP_SUB_SBC [2]
-`define FIELD_ALUOP_RSB_RSC [2]
-`define FIELD_ALUOP_ADD_CMN [1]
-`define FIELD_ALUOP_ADD_NOTCMN_ADC [0]
-
-// Segundo operando de varios grupos de instrucciones
-
-`define FIELD_SND_ROR8 [11:8]
-`define FIELD_SND_IMM8 [7:0]
-`define FIELD_SND_IMM12 [11:0]
-`define FIELD_SND_SHIFTIMM [11:7]
-`define FIELD_SND_RS [11:8]
-`define FIELD_SND_ZEROIFREG [7]
-`define FIELD_SND_SHIFT [6:5]
-`define FIELD_SND_RM [3:0]
-
-`define SHIFT_LSL 2'b00
-`define SHIFT_LSR 2'b01
-`define SHIFT_ASR 2'b10
-`define SHIFT_ROR 2'b11
-
-// Instrucciones de salto
-
-`define INSN_B 28'b101_0_????????????????????????
-`define INSN_BL 28'b101_1_????????????????????????
-
-// Esto no es parte de ARMv4, pero U-boot tiene algunos `bx lr` hard-coded
-`define INSN_BXLR 28'h12fff1e
-
-`define GROUP_B 28'b101_?_????????????????????????
-
-`define FIELD_B_L [24]
-`define FIELD_B_OFFSET [23:0]
-
-// Instrucciones de procesamiento de datos (aritmético-lógicas y MOV)
-
-`define INSN_AND 28'b00_?_0000_?_????_????_????????????
-`define INSN_EOR 28'b00_?_0001_?_????_????_????????????
-`define INSN_SUB 28'b00_?_0010_?_????_????_????????????
-`define INSN_RSB 28'b00_?_0011_?_????_????_????????????
-`define INSN_ADD 28'b00_?_0100_?_????_????_????????????
-`define INSN_ADC 28'b00_?_0101_?_????_????_????????????
-`define INSN_SBC 28'b00_?_0110_?_????_????_????????????
-`define INSN_RSC 28'b00_?_0111_?_????_????_????????????
-`define INSN_TST 28'b00_?_1000_1_????_0000_????????????
-`define INSN_TEQ 28'b00_?_1001_1_????_0000_????????????
-`define INSN_CMP 28'b00_?_1010_1_????_0000_????????????
-`define INSN_CMN 28'b00_?_1011_1_????_0000_????????????
-`define INSN_ORR 28'b00_?_1100_?_????_????_????????????
-`define INSN_MOV 28'b00_?_1101_?_0000_????_????????????
-`define INSN_BIC 28'b00_?_1110_?_????_????_????????????
-`define INSN_MVN 28'b00_?_1111_?_0000_????_????????????
-
-`define GROUP_ALU \
- `INSN_AND, `INSN_EOR, `INSN_SUB, `INSN_RSB, `INSN_ADD, `INSN_ADC, `INSN_SBC, `INSN_RSC, \
- `INSN_TST, `INSN_TEQ, `INSN_CMP, `INSN_CMN, `INSN_ORR, `INSN_MOV, `INSN_BIC, `INSN_MVN
-
-`define FIELD_DATA_IMM [25]
-`define FIELD_DATA_OPCODE [24:21]
-`define FIELD_DATA_S [20]
-`define FIELD_DATA_RN [19:16]
-`define FIELD_DATA_RD [15:12]
-`define FIELD_DATA_REGSHIFT [4]
-
-// Instrucciones de multiplicación
-
-`define INSN_MUL 28'b0000000_?_????_0000_????_1001_????
-`define INSN_MLA 28'b0000001_?_????_????_????_1001_????
-`define INSN_UMULL 28'b0000100_?_????_????_????_1001_????
-`define INSN_UMLAL 28'b0000101_?_????_????_????_1001_????
-`define INSN_SMULL 28'b0000110_?_????_????_????_1001_????
-`define INSN_SMLAL 28'b0000111_?_????_????_????_1001_????
-
-`define GROUP_MUL `INSN_MUL, `INSN_MLA, `INSN_UMULL, `INSN_UMLAL, `INSN_SMULL, `INSN_SMLAL
-
-`define FIELD_MUL_LONG [23]
-`define FIELD_MUL_SIGNED [22]
-`define FIELD_MUL_ACC [21]
-`define FIELD_MUL_S [20]
-`define FIELD_MUL_RD [19:16]
-`define FIELD_MUL_RN [15:12]
-`define FIELD_MUL_RS [11:8]
-`define FIELD_MUL_RM [3:0]
-
-// Instrucciones de load/store
-
-`define INSN_LDR 28'b01_?_?_?_0_?_1_????_????_????????????
-`define INSN_LDRB 28'b01_?_?_?_1_?_1_????_????_????????????
-`define INSN_LDRBT 28'b01_?_0_?_1_1_1_????_????_????????????
-`define INSN_LDRT 28'b01_?_0_?_0_1_1_????_????_????????????
-`define INSN_STR 28'b01_?_?_?_0_?_0_????_????_????????????
-`define INSN_STRB 28'b01_?_?_?_1_?_0_????_????_????????????
-`define INSN_STRBT 28'b01_?_0_?_1_1_0_????_????_????????????
-`define INSN_STRT 28'b01_?_0_?_0_1_0_????_????_????????????
-
-`define INSN_LDRH 28'b000_?_?_?_?_1_????_????_????_1011_????
-`define INSN_LDRSB 28'b000_?_?_?_?_1_????_????_????_1101_????
-`define INSN_LDRSH 28'b000_?_?_?_?_1_????_????_????_1111_????
-`define INSN_STRH 28'b000_?_?_?_?_0_????_????_????_1011_????
-
-`define INSN_LDM_CUR 28'b100_?_?_0_?_1_????_????????????????
-`define INSN_LDM_USR 28'b100_?_?_1_0_1_????_0_???????????????
-`define INSN_LDM_RFE 28'b100_?_?_1_?_1_????_1_???????????????
-`define INSN_STM_CUR 28'b100_?_?_0_?_0_????_????????????????
-`define INSN_STM_USR 28'b100_?_?_1_0_0_????_????????????????
-
-`define GROUP_LDST_SINGLE_IMM 28'b01_0_?_?_?_?_?_????_????_????????????
-`define GROUP_LDST_SINGLE_REG 28'b01_1_?_?_?_?_?_????_????_?????_??_0_????
-`define GROUP_LDST_SINGLE `GROUP_LDST_SINGLE_IMM, `GROUP_LDST_SINGLE_REG
-`define GROUP_LDST_MISC `INSN_LDRH, `INSN_LDRSB, `INSN_LDRSH, `INSN_STRH
-`define GROUP_LDST_MULT 28'b100_?_?_?_?_?_????_????????????????
-
-`define FIELD_LDST_LD [20]
-`define FIELD_LDST_SINGLE_REG [25]
-`define FIELD_LDST_SINGLE_P [24]
-`define FIELD_LDST_SINGLE_U [23]
-`define FIELD_LDST_SINGLE_B [22]
-`define FIELD_LDST_SINGLE_W [21]
-`define FIELD_LDST_SINGLE_RN [19:16]
-`define FIELD_LDST_SINGLE_RD [15:12]
-
-`define FIELD_LDST_MISC_P [24]
-`define FIELD_LDST_MISC_U [23]
-`define FIELD_LDST_MISC_IMM [22]
-`define FIELD_LDST_MISC_W [21]
-`define FIELD_LDST_MISC_RN [19:16]
-`define FIELD_LDST_MISC_RD [15:12]
-`define FIELD_LDST_MISC_IMM_HI [11:8]
-`define FIELD_LDST_MISC_S [6]
-`define FIELD_LDST_MISC_H [5]
-`define FIELD_LDST_MISC_IMM_LO [3:0]
-`define FIELD_LDST_MISC_RM [3:0]
-
-`define FIELD_LDST_MULT_P [24]
-`define FIELD_LDST_MULT_U [23]
-`define FIELD_LDST_MULT_S [22]
-`define FIELD_LDST_MULT_W [21]
-`define FIELD_LDST_MULT_RN [19:16]
-`define FIELD_LDST_MULT_LIST [15:0]
-
-// Instrucciones para operaciones atómicas optimistas (monitor exclusivo)
-
-`define INSN_LDREX 28'b0001100_1_????_????_1111_1001_1111
-`define INSN_STREX 28'b0001100_0_????_????_1111_1001_????
-`define GROUP_LDST_EX `INSN_LDREX, `INSN_STREX
-
-`define FIELD_LDST_EX_LD [20]
-`define FIELD_LDST_EX_RN [19:16]
-`define FIELD_LDST_EX_RD [15:12]
-`define FIELD_LDST_EX_R_OK [3:0]
-
-// Instrucciones atómicas de intercambio registro-memoria (deprecadas)
-
-`define INSN_SWP 28'b00010000_????_????_0000_1001_????
-`define INSN_SWPB 28'b00010100_????_????_0000_1001_????
-
-`define GROUP_SWP 28'b00010?00_????_????_0000_1001_????
-
-`define FIELD_SWP_BYTE [22]
-`define FIELD_SWP_RN [19:16]
-`define FIELD_SWP_RD [15:12]
-`define FIELD_SWP_RM [3:0]
-
-// Instrucciones de coprocesador, solo definido para CP15
-
-`define INSN_MCR 28'b1110_???_0_????_????_1111_???_1_????
-`define INSN_MRC 28'b1110_???_1_????_????_1111_???_1_????
-
-`define GROUP_CP 28'b1110_???_?_????_????_1111_???_1_????
-
-`define FIELD_CP_OPCODE [23:21]
-`define FIELD_CP_LOAD [20]
-`define FIELD_CP_CRN [19:16]
-`define FIELD_CP_RD [15:12]
-`define FIELD_CP_NUM [11:8]
-`define FIELD_CP_OPCODE2 [7:5]
-`define FIELD_CP_CRM [3:0]
-
-// Instrucciones de CPSR/SPSR
-
-`define INSN_MRS 28'b0_0_0_1_0_?_0_0_1111_????_000000000000
-`define INSN_MSR_IMM 28'b0_0_1_1_0_?_1_0_????_1111_????_????????
-`define INSN_MSR_REG 28'b0_0_0_1_0_?_1_0_????_1111_0000_0000_????
-
-`define GROUP_MSR `INSN_MSR_IMM, `INSN_MSR_REG
-
-`define FIELD_MRS_R [22]
-`define FIELD_MRS_RD [15:12]
-`define FIELD_MSR_I [25]
-`define FIELD_MSR_R [22]
-`define FIELD_MSR_MASK [19:16]
-
-// System call
-
-`define INSN_SWI 28'b1111_????????????????????????
-
-`define FIELD_SWI_IMM [23:0]
-
-// GDB swbreak (a magic 'und')
-
-`define INSN_GDB_SWBREAK 28'h7ffdefe
-
-`endif
diff --git a/rtl/core/decode/ldst/addr.sv b/rtl/core/decode/ldst/addr.sv
deleted file mode 100644
index 345f0ea..0000000
--- a/rtl/core/decode/ldst/addr.sv
+++ /dev/null
@@ -1,15 +0,0 @@
-`include "core/uarch.sv"
-
-module core_decode_ldst_addr
-(
- input ldst_decode ldst,
-
- output data_decode alu
-);
-
- assign alu.op = ldst.increment ? `ALU_ADD : `ALU_SUB;
- assign alu.rn = ldst.rn;
- assign alu.rd = ldst.rd;
- assign alu.uses_rn = 1;
-
-endmodule
diff --git a/rtl/core/decode/ldst/exclusive.sv b/rtl/core/decode/ldst/exclusive.sv
deleted file mode 100644
index 7942a04..0000000
--- a/rtl/core/decode/ldst/exclusive.sv
+++ /dev/null
@@ -1,27 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_ldst_exclusive
-(
- input word insn,
-
- output ldst_decode decode,
- output reg_num snd_r
-);
-
- assign snd_r = insn `FIELD_LDST_EX_R_OK;
-
- assign decode.rn = insn `FIELD_LDST_EX_RN;
- assign decode.rd = insn `FIELD_LDST_EX_RD;
- assign decode.size = LDST_WORD;
- assign decode.load = insn `FIELD_LDST_EX_LD;
- assign decode.increment = 0;
- assign decode.writeback = 0;
- assign decode.exclusive = 1;
- assign decode.sign_extend = 0;
- assign decode.pre_indexed = 0;
- assign decode.unprivileged = 0;
- assign decode.user_regs = 0;
- assign decode.regs = 16'b0;
-
-endmodule
diff --git a/rtl/core/decode/ldst/misc.sv b/rtl/core/decode/ldst/misc.sv
deleted file mode 100644
index 72d648c..0000000
--- a/rtl/core/decode/ldst/misc.sv
+++ /dev/null
@@ -1,36 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_ldst_misc
-(
- input word insn,
-
- output ldst_decode decode,
- output logic off_is_imm,
- output logic[7:0] off_imm,
- output reg_num off_reg
-);
-
- logic p, w;
-
- assign decode.rn = insn `FIELD_LDST_MISC_RN;
- assign decode.rd = insn `FIELD_LDST_MISC_RD;
- assign decode.size = insn `FIELD_LDST_MISC_H ? LDST_HALF : LDST_BYTE;
- assign decode.load = insn `FIELD_LDST_LD;
- assign decode.increment = insn `FIELD_LDST_MISC_U;
- assign decode.writeback = !p || w;
- assign decode.exclusive = 0;
- assign decode.sign_extend = insn `FIELD_LDST_MISC_S;
- assign decode.pre_indexed = p;
- assign decode.unprivileged = 0;
- assign decode.user_regs = 0;
- assign decode.regs = 16'b0;
-
- assign off_imm = {insn `FIELD_LDST_MISC_IMM_HI, insn `FIELD_LDST_MISC_IMM_LO};
- assign off_reg = insn `FIELD_LDST_MISC_RM;
- assign off_is_imm = insn `FIELD_LDST_MISC_IMM;
-
- assign p = insn `FIELD_LDST_MISC_P;
- assign w = insn `FIELD_LDST_MISC_W;
-
-endmodule
diff --git a/rtl/core/decode/ldst/multiple.sv b/rtl/core/decode/ldst/multiple.sv
deleted file mode 100644
index c822ab0..0000000
--- a/rtl/core/decode/ldst/multiple.sv
+++ /dev/null
@@ -1,34 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_ldst_multiple
-(
- input word insn,
-
- output ldst_decode decode,
- output logic restore_spsr
-);
-
- logic s, l;
- reg_list regs;
-
- assign decode.rn = insn `FIELD_LDST_MULT_RN;
- assign decode.rd = 4'bxxxx;
- assign decode.size = LDST_WORD;
- assign decode.load = l;
- assign decode.increment = insn `FIELD_LDST_MULT_U;
- assign decode.writeback = insn `FIELD_LDST_MULT_W;
- assign decode.exclusive = 0;
- assign decode.sign_extend = 0;
- assign decode.pre_indexed = insn `FIELD_LDST_MULT_P;
- assign decode.unprivileged = 0;
- assign decode.user_regs = s && !(l && regs[`R15]);
- assign decode.regs = regs;
-
- assign s = insn `FIELD_LDST_MULT_S;
- assign l = insn `FIELD_LDST_LD;
-
- assign regs = insn `FIELD_LDST_MULT_LIST;
- assign restore_spsr = s && l && regs[`R15];
-
-endmodule
diff --git a/rtl/core/decode/ldst/single.sv b/rtl/core/decode/ldst/single.sv
deleted file mode 100644
index af096a7..0000000
--- a/rtl/core/decode/ldst/single.sv
+++ /dev/null
@@ -1,31 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_ldst_single
-(
- input word insn,
-
- output ldst_decode decode,
- output logic snd_is_imm
-);
-
- logic p, w;
-
- assign decode.rn = insn `FIELD_LDST_SINGLE_RN;
- assign decode.rd = insn `FIELD_LDST_SINGLE_RD;
- assign decode.size = insn `FIELD_LDST_SINGLE_B ? LDST_BYTE : LDST_WORD;
- assign decode.load = insn `FIELD_LDST_LD;
- assign decode.increment = insn `FIELD_LDST_SINGLE_U;
- assign decode.writeback = !p || w;
- assign decode.exclusive = 0;
- assign decode.sign_extend = 0;
- assign decode.pre_indexed = p;
- assign decode.unprivileged = !p && w;
- assign decode.user_regs = 0;
- assign decode.regs = 16'b0;
-
- assign p = insn `FIELD_LDST_SINGLE_P;
- assign w = insn `FIELD_LDST_SINGLE_W;
- assign snd_is_imm = !insn `FIELD_LDST_SINGLE_REG;
-
-endmodule
diff --git a/rtl/core/decode/mrs.sv b/rtl/core/decode/mrs.sv
deleted file mode 100644
index 05018cd..0000000
--- a/rtl/core/decode/mrs.sv
+++ /dev/null
@@ -1,15 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_mrs
-(
- input word insn,
-
- output reg_num rd,
- output logic spsr
-);
-
- assign rd = insn `FIELD_MRS_RD;
- assign spsr = insn `FIELD_MRS_R;
-
-endmodule
diff --git a/rtl/core/decode/msr.sv b/rtl/core/decode/msr.sv
deleted file mode 100644
index c3f0e3d..0000000
--- a/rtl/core/decode/msr.sv
+++ /dev/null
@@ -1,17 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_msr
-(
- input word insn,
-
- output msr_mask fields,
- output logic spsr,
- snd_is_imm
-);
-
- assign spsr = insn `FIELD_MSR_R;
- assign fields = insn `FIELD_MSR_MASK;
- assign snd_is_imm = insn `FIELD_MSR_I;
-
-endmodule
diff --git a/rtl/core/decode/mul_dec.sv b/rtl/core/decode/mul_dec.sv
deleted file mode 100644
index 114b65b..0000000
--- a/rtl/core/decode/mul_dec.sv
+++ /dev/null
@@ -1,33 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_mul
-(
- input word insn,
-
- output mul_decode decode,
- output reg_num rd,
- rs,
- rm,
- output logic update_flags
-);
-
- logic long_mul;
- reg_num short_rd, rn;
-
- assign rd = long_mul ? rn : short_rd;
- assign rs = insn `FIELD_MUL_RS;
- assign rm = insn `FIELD_MUL_RM;
- assign update_flags = insn `FIELD_MUL_S;
-
- assign decode.add = insn `FIELD_MUL_ACC;
- assign decode.long_mul = long_mul;
- assign decode.signed_mul = insn `FIELD_MUL_SIGNED;
- assign decode.r_add_lo = rn;
- assign decode.r_add_hi = short_rd;
-
- assign long_mul = insn `FIELD_MUL_LONG;
- assign short_rd = insn `FIELD_MUL_RD;
- assign rn = insn `FIELD_MUL_RN;
-
-endmodule
diff --git a/rtl/core/decode/mux.sv b/rtl/core/decode/mux.sv
deleted file mode 100644
index 6f0451a..0000000
--- a/rtl/core/decode/mux.sv
+++ /dev/null
@@ -1,295 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_mux
-(
- input word insn,
-
- input logic branch_link,
-
- input snd_decode snd,
- input logic snd_undefined,
-
- input data_decode data,
- input logic data_writeback,
- data_conditional,
- data_update_flags,
- data_restore_spsr,
- data_is_imm,
- data_shift_by_reg_if_reg,
-
- input ldst_decode ldst_misc,
- ldst_single,
- ldst_multiple,
- ldst_exclusive,
- input logic ldst_single_is_imm,
- ldst_misc_off_is_imm,
- input reg_num ldst_ex_snd_r,
- ldst_misc_off_reg,
- input logic[7:0] ldst_misc_off_imm,
- input logic ldst_mult_restore_spsr,
- input data_decode data_ldst,
-
- input logic mul_update_flags,
- input reg_num mul_rd,
- mul_rs,
- mul_rm,
-
- input coproc_decode dec_coproc,
- input logic coproc_writeback,
- coproc_update_flags,
- input reg_num coproc_rd,
-
- input logic msr_spsr,
- msr_is_imm,
- mrs_spsr,
- input reg_num mrs_rd,
- input msr_mask msr_fields,
-
- output snd_decode dec_snd,
- output data_decode dec_data,
- output ldst_decode dec_ldst,
- ldst_addr,
- output logic execute,
- undefined,
- conditional,
- writeback,
- branch,
- ldst,
- mul,
- psr,
- swi,
- coproc,
- bkpt,
- psr_saved,
- psr_write,
- psr_wr_flags,
- psr_wr_control,
- update_flags,
- restore_spsr,
- snd_is_imm,
- snd_ror_if_imm,
- snd_shift_by_reg_if_reg
-);
-
- always_comb begin
- mul = 0;
- swi = 0;
- psr = 0;
- ldst = 0;
- bkpt = 0;
- branch = 0;
- coproc = 0;
- execute = 1;
- undefined = 0;
- writeback = 0;
- conditional = 0;
- restore_spsr = 0;
-
- psr_saved = 0;
- psr_write = 0;
- update_flags = 0;
- psr_wr_flags = 1;
- psr_wr_control = 1;
-
- dec_data = {($bits(dec_data)){1'bx}};
- dec_data.uses_rn = 1;
-
- dec_snd = {$bits(dec_snd){1'bx}};
- dec_snd.shr = 0;
- dec_snd.ror = 0;
- dec_snd.is_imm = 1;
- dec_snd.shift_imm = {$bits(dec_snd.shift_imm){1'b0}};
- dec_snd.shift_by_reg = 0;
-
- snd_is_imm = 1'bx;
- snd_ror_if_imm = 1'bx;
- snd_shift_by_reg_if_reg = 1'bx;
-
- dec_ldst = {($bits(dec_ldst)){1'bx}};
- ldst_addr = {($bits(ldst_addr)){1'bx}};
-
- // El orden de los casos es importante, NO CAMBIAR
- priority casez(insn `FIELD_OP)
- `GROUP_B: begin
- branch = 1;
- dec_data.uses_rn = branch_link;
-
- if(branch_link) begin
- dec_data.op = `ALU_SUB;
- dec_data.rd = `R14;
- dec_data.rn = `R15;
- dec_snd.imm = 12'd4;
- writeback = 1;
- end
- end
-
- `GROUP_MUL: begin
- mul = 1;
-
- dec_data.rd = mul_rd;
- dec_data.rn = mul_rs;
-
- dec_snd.is_imm = 0;
- dec_snd.r = mul_rm;
-
- writeback = 1;
- update_flags = mul_update_flags;
- end
-
- `GROUP_LDST_EX: begin
- dec_ldst = ldst_exclusive;
- ldst_addr = ldst_exclusive;
-
- dec_snd.r = ldst_ex_snd_r;
- dec_snd.is_imm = ldst_exclusive.load;
- end
-
- `GROUP_LDST_MISC: begin
- dec_ldst = ldst_misc;
- ldst_addr = ldst_misc;
-
- dec_snd.r = ldst_misc_off_reg;
- dec_snd.imm = {4'b0, ldst_misc_off_imm};
- dec_snd.is_imm = ldst_misc_off_is_imm;
- end
-
- `GROUP_ALU: begin
- snd_is_imm = data_is_imm;
- snd_ror_if_imm = 1;
- snd_shift_by_reg_if_reg = data_shift_by_reg_if_reg;
-
- dec_snd = snd;
- dec_data = data;
-
- writeback = data_writeback;
- update_flags = data_update_flags;
- restore_spsr = data_restore_spsr;
-
- undefined = snd_undefined;
- conditional = data_conditional;
- end
-
- `GROUP_LDST_SINGLE: begin
- snd_is_imm = ldst_single_is_imm;
- snd_ror_if_imm = 0;
- snd_shift_by_reg_if_reg = 0;
-
- dec_snd = snd;
- dec_ldst = ldst_single;
- ldst_addr = ldst_single;
-
- undefined = snd_undefined;
- end
-
- `GROUP_LDST_MULT: begin
- dec_ldst = ldst_multiple;
- ldst_addr = ldst_multiple;
- dec_snd.imm = 12'd4;
-
- restore_spsr = ldst_mult_restore_spsr;
- end
-
- `GROUP_CP: begin
- coproc = 1;
- writeback = coproc_writeback;
- update_flags = coproc_update_flags;
-
- dec_data.op = `ALU_MOV;
- dec_data.rn = coproc_rd;
- dec_data.rd = coproc_rd;
- dec_data.uses_rn = dec_coproc.load;
- end
-
- `INSN_MRS: begin
- dec_data.rd = mrs_rd;
- dec_data.uses_rn = 0;
-
- psr = 1;
- psr_saved = mrs_spsr;
- writeback = 1;
- conditional = 1;
- end
-
- `GROUP_MSR: begin
- dec_data.uses_rn = 0;
-
- snd_is_imm = msr_is_imm;
- snd_ror_if_imm = 1;
- snd_shift_by_reg_if_reg = 0;
-
- psr = 1;
- dec_snd = snd;
- psr_write = 1;
- psr_saved = msr_spsr;
- conditional = 1;
- psr_wr_flags = msr_fields.f;
- psr_wr_control = msr_fields.c;
- end
-
- // WONTFIX: <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=9757>
- //`GROUP_SWP: ;
-
- `INSN_SWI: begin
- swi = 1;
- dec_data.uses_rn = 0;
- end
-
- /* No es parte de ARMv4 pero U-Boot lo necesita. esto se
- * decodifica igual que `mov pc, lr` ya que no tenemos Thumb.
- */
- `INSN_BXLR: begin
- dec_data.op = `ALU_MOV;
- dec_data.rd = `R15;
- dec_data.uses_rn = 0;
-
- dec_snd.r = `R14;
- dec_snd.is_imm = 0;
-
- writeback = 1;
- end
-
-`ifdef VERILATOR
- // No es parte de ARM del todo, es un hack para soportar gdb
- `INSN_GDB_SWBREAK: begin
- bkpt = 1;
- dec_data.uses_rn = 0;
- end
-`endif
-
- default:
- undefined = 1;
- endcase
-
- unique casez(insn `FIELD_OP)
- // Codificación coincide con ldst
- `GROUP_MUL: ;
-
- `GROUP_LDST_SINGLE, `GROUP_LDST_MISC, `GROUP_LDST_MULT, `GROUP_LDST_EX: begin
- ldst = 1;
- dec_data = data_ldst;
- writeback = dec_ldst.writeback || dec_ldst.load || dec_ldst.exclusive;
- end
-
- default: ;
- endcase
-
- if(undefined) begin
- execute = 0;
-
- mul = 1'bx;
- psr = 1'bx;
- ldst = 1'bx;
- branch = 1'bx;
- coproc = 1'bx;
- writeback = 1'bx;
- conditional = 1'bx;
- update_flags = 1'bx;
-
- dec_snd = {($bits(dec_snd)){1'bx}};
- dec_data = {($bits(dec_data)){1'bx}};
- dec_ldst = {($bits(dec_ldst)){1'bx}};
- end
- end
-
-endmodule
diff --git a/rtl/core/decode/snd.sv b/rtl/core/decode/snd.sv
deleted file mode 100644
index 264982e..0000000
--- a/rtl/core/decode/snd.sv
+++ /dev/null
@@ -1,75 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_snd
-(
- input word insn,
- input logic is_imm,
- ror_if_imm,
- shift_by_reg_if_reg,
-
- output snd_decode decode,
- output logic undefined
-);
-
- reg_num r, r_shift;
- logic shift_by_reg, shr, ror, put_carry, sign_extend;
- logic[11:0] imm;
- logic[5:0] shift_imm;
-
- assign decode.r = r;
- assign decode.r_shift = r_shift;
- assign decode.shift_by_reg = shift_by_reg;
- assign decode.is_imm = is_imm;
- assign decode.shr = shr;
- assign decode.ror = ror;
- assign decode.put_carry = put_carry;
- assign decode.sign_extend = sign_extend;
- assign decode.imm = imm;
- assign decode.shift_imm = shift_imm;
-
- assign r = insn `FIELD_SND_RM;
- assign r_shift = insn `FIELD_SND_RS;
- assign imm = ror_if_imm ? {4'b0, insn `FIELD_SND_IMM8} : insn `FIELD_SND_IMM12;
- assign shift_by_reg = ~is_imm & shift_by_reg_if_reg;
- assign undefined = shift_by_reg & insn `FIELD_SND_ZEROIFREG;
-
- logic[1:0] shift_op;
- assign shift_op = insn `FIELD_SND_SHIFT;
-
- always_comb begin
- ror = is_imm;
- shr = ~is_imm;
- put_carry = 0;
- sign_extend = 0;
-
- if(is_imm)
- shift_imm = ror_if_imm ? {1'b0, insn `FIELD_SND_ROR8, 1'b0} : 6'b0;
- else begin
- shift_imm = {1'b0, insn `FIELD_SND_SHIFTIMM};
-
- case(shift_op)
- `SHIFT_LSL: shr = 0;
- `SHIFT_LSR: ;
- `SHIFT_ASR: sign_extend = 1;
- `SHIFT_ROR: ror = 1;
- endcase
-
- if(!shift_by_reg && shift_imm == 0)
- case(shift_op)
- `SHIFT_LSL: ;
-
- `SHIFT_LSR, `SHIFT_ASR:
- shift_imm = 6'd32;
-
- `SHIFT_ROR: begin
- // RRX
- ror = 0;
- shift_imm = 6'd1;
- put_carry = 1;
- end
- endcase
- end
- end
-
-endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-18 15:06:23 +0000