4 files changed, 55 insertions, 29 deletions

diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/cp15/cp15.sv
index bf84292..f0391e8 100644
--- a/rtl/core/cp15/cp15.sv
+++ b/rtl/core/cp15/cp15.sv
@@ -4,19 +4,23 @@
 
 module core_cp15
 (
-	input  logic         clk,
-	                     rst_n,
-	                     transfer,
-	input  coproc_decode dec,
-	input  word          write,
-
-	input  logic         fault_register,
-	input  ptr           fault_addr,
-
-	output word          read,
-	output logic         high_vectors,
-	                     mmu_enable,
-	output mmu_base      mmu_ttbr
+	input  logic          clk,
+	                      rst_n,
+	                      transfer,
+	input  coproc_decode  dec,
+	input  word           write,
+
+	input  logic          fault_register,
+	                      fault_page,
+	input  ptr            fault_addr,
+	input  mmu_fault_type fault_type,
+	input  mmu_domain     fault_domain,
+
+	output word           read,
+	                      mmu_dac,
+	output logic          high_vectors,
+	                      mmu_enable,
+	output mmu_base       mmu_ttbr
 );
 
 	logic load;
diff --git a/rtl/core/cp15/domain.sv b/rtl/core/cp15/domain.sv
index 4e5f5d6..92112be 100644
--- a/rtl/core/cp15/domain.sv
+++ b/rtl/core/cp15/domain.sv
@@ -9,16 +9,16 @@ module core_cp15_domain
 	                 transfer,
 	input  word      write,
 
-	output word      read
+	output word      read,
+	                 mmu_dac
 );
 
-	word dac;
-	assign read = dac;
+	assign read = mmu_dac;
 
 	always @(posedge clk or negedge rst_n)
 		if(!rst_n)
-			dac <= 0;
+			mmu_dac <= 0;
 		else if(transfer && !load)
-			dac <= write;
+			mmu_dac <= write;
 
 endmodule
diff --git a/rtl/core/cp15/far.sv b/rtl/core/cp15/far.sv
index 3d86151..9e1d95c 100644
--- a/rtl/core/cp15/far.sv
+++ b/rtl/core/cp15/far.sv
@@ -8,7 +8,6 @@ module core_cp15_far
 
 	input  logic     load,
 	                 transfer,
-	input  cp_opcode op2,
 	input  word      write,
 
 	input  logic     fault_register,
diff --git a/rtl/core/cp15/fsr.sv b/rtl/core/cp15/fsr.sv
index 0a7d0d4..c42d16a 100644
--- a/rtl/core/cp15/fsr.sv
+++ b/rtl/core/cp15/fsr.sv
@@ -1,20 +1,43 @@
-`include "core/uarch.sv"
 `include "core/cp15/map.sv"
+`include "core/mmu/format.sv"
+`include "core/uarch.sv"
 
 module core_cp15_fsr
 (
-	input  logic     clk,
-	                 rst_n,
+	input  logic          clk,
+	                      rst_n,
+
+	input  logic          load,
+	                      transfer,
+	input  word           write,
 
-	input  logic     load,
-	                 transfer,
-	input  cp_opcode op2,
-	input  word      write,
+	input  logic          fault_register,
+	                      fault_page,
+	input  mmu_fault_type fault_type,
+	input  mmu_domain     fault_domain,
 
-	output word      read
+	output word           read
 );
 
-	//TODO
-	assign read = 0;
+	logic fsr_page;
+	mmu_domain fsr_domain;
+	mmu_fault_type fsr_type;
+
+	assign read = {24'd0, fsr_domain, fsr_type, fsr_page, 1'b1};
+
+	always @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			fsr_page <= 0;
+			fsr_type <= 0;
+			fsr_domain <= 0;
+		end else if(fault_register) begin
+			fsr_page <= fault_page;
+			fsr_type <= fault_type;
+			fsr_domain <= fault_domain;
+		end else if(transfer && !load) begin
+			fsr_page <= write[1];
+			fsr_type <= write[3:2];
+			fsr_domain <= write[7:4];
+		end
 
 endmodule