2 files changed, 78 insertions, 64 deletions

diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index cedf3cf..3c0ec6c 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -22,36 +22,44 @@ module core_control_select
 	output psr_mode    reg_mode
 );
 
-	reg_num r_shift;
+	reg_num r_shift, last_ra, last_rb;
 
 	assign reg_mode = `MODE_SVC; //TODO
 
-	always_ff @(posedge clk)
+	always_comb begin
+		ra = last_ra;
+		rb = last_rb;
+
 		unique case(next_cycle)
 			ISSUE:
 				if(issue) begin
-					ra <= dec_data.rn;
-					rb <= dec_snd.r;
-					r_shift <= dec_snd.r_shift;
+					ra = dec_data.rn;
+					rb = dec_snd.r;
 				end
 
-			RD_INDIRECT_SHIFT:
-				rb <= r_shift;
-
 			TRANSFER:
 				if(cycle != TRANSFER || mem_ready)
 					// final_rd viene de dec_ldst.rd
-					rb <= pop_valid ? popped : final_rd;
+					rb = pop_valid ? popped : final_rd;
 
 			MUL_ACC_LD: begin
-				ra <= mul_r_add_hi;
-				rb <= mul_r_add_lo;
+				ra = mul_r_add_hi;
+				rb = mul_r_add_lo;
 			end
 		endcase
+	end
+
+	always_ff @(posedge clk) begin
+		last_ra <= ra;
+		last_rb <= rb;
+
+		if(next_cycle == ISSUE && issue)
+			r_shift <= dec_snd.r_shift;
+	end
 
 	initial begin
-		ra = {$bits(ra){1'b0}};
-		rb = {$bits(rb){1'b0}};
+		last_ra = {$bits(ra){1'b0}};
+		last_rb = {$bits(rb){1'b0}};
 		r_shift = {$bits(r_shift){1'b0}};
 	end
 
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 733881c..a4465ff 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -35,53 +35,91 @@ module core_control_writeback
 	output psr_flags       wb_alu_flags
 );
 
-	always_ff @(posedge clk) begin
-		wb_alu_flags <= alu_flags;
+	reg_num last_rd;
 
+	always_comb begin
+		rd = last_rd;
 		unique case(next_cycle)
 			TRANSFER:
 				if(mem_ready)
-					rd <= final_rd;
+					rd = final_rd;
 
 			ISSUE, BASE_WRITEBACK:
-				rd <= final_rd;
+				rd = final_rd;
 
 			EXCEPTION:
-				rd <= `R15;
+				rd = `R15;
 
 			MUL_HI_WB:
-				rd <= mul_r_add_hi;
+				rd = mul_r_add_hi;
 		endcase
 
 		unique case(next_cycle)
 			ISSUE:
-				if(issue)
-					final_rd <= dec_data.rd;
+				writeback = final_writeback;
 
 			TRANSFER:
-				if((cycle != TRANSFER || mem_ready) && pop_valid)
-					final_rd <= popped;
+				writeback = mem_ready && !mem_write;
 
 			BASE_WRITEBACK:
-				final_rd <= ra;
+				writeback = !mem_write;
+
+			EXCEPTION, MUL_HI_WB:
+				writeback = 1;
+
+			default:
+				writeback = 0;
+		endcase
+
+		unique case(cycle)
+			TRANSFER:
+				wr_value = mem_data_rd;
+
+			BASE_WRITEBACK:
+				wr_value = saved_base;
+
+			MUL, MUL_HI_WB:
+				wr_value = mul_q_lo;
+
+			default:
+				// Ruta combinacional larga
+				wr_value = q_alu;
+		endcase
+
+		unique case(next_cycle)
+			TRANSFER:
+				if(mem_ready)
+					wr_value = mem_data_rd;
+
+			BASE_WRITEBACK:
+				wr_value = mem_data_rd;
 
 			EXCEPTION:
-				final_rd <= `R14;
+				wr_value = vector;
+
+			MUL_HI_WB:
+				wr_value = mul_q_hi;
 		endcase
+	end
+
+	always_ff @(posedge clk) begin
+		last_rd <= rd;
+		wb_alu_flags <= alu_flags;
 
-		writeback <= 0;
 		unique case(next_cycle)
 			ISSUE:
-				writeback <= final_writeback;
+				if(issue)
+					final_rd <= dec_data.rd;
 
 			TRANSFER:
-				writeback <= mem_ready && !mem_write;
+				if((cycle != TRANSFER || mem_ready) && pop_valid)
+					final_rd <= popped;
 
 			BASE_WRITEBACK:
-				writeback <= !mem_write;
+				final_rd <= ra;
 
-			EXCEPTION, MUL_HI_WB:
-				writeback <= 1;
+			EXCEPTION:
+				final_rd <= `R14;
 		endcase
 
 		unique case(next_cycle)
@@ -108,48 +146,16 @@ module core_control_writeback
 			EXCEPTION:
 				final_update_flags <= 0;
 		endcase
-
-		unique case(cycle)
-			TRANSFER:
-				wr_value <= mem_data_rd;
-
-			BASE_WRITEBACK:
-				wr_value <= saved_base;
-
-			MUL, MUL_HI_WB:
-				wr_value <= mul_q_lo;
-
-			default:
-				wr_value <= q_alu;
-		endcase
-
-		unique case(next_cycle)
-			TRANSFER:
-				if(mem_ready)
-					wr_value <= mem_data_rd;
-
-			BASE_WRITEBACK:
-				wr_value <= mem_data_rd;
-
-			EXCEPTION:
-				wr_value <= vector;
-
-			MUL_HI_WB:
-				wr_value <= mul_q_hi;
-		endcase
 	end
 
 	initial begin
-		rd = 0;
+		last_rd = 0;
 		final_rd = 0;
-
-		writeback = 0;
 		final_writeback = 0;
 
 		update_flags = 0;
 		final_update_flags = 0;
 
-		wr_value = 0;
 		wb_alu_flags = {$bits(wb_alu_flags){1'b0}};
 	end