diff options
Diffstat (limited to 'rtl/core/control')
| -rw-r--r-- | rtl/core/control/control.sv | 3 | ||||
| -rw-r--r-- | rtl/core/control/exception.sv | 6 | ||||
| -rw-r--r-- | rtl/core/control/issue.sv | 6 |
3 files changed, 12 insertions, 3 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 8bf4976..840cf19 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -9,6 +9,7 @@ module core_control input insn_decode dec, input ptr insn_pc, + input logic issue_abort, input psr_mode mode, input psr_flags flags, alu_flags, @@ -89,7 +90,7 @@ module core_control ); ptr pc /*verilator public*/, next_pc_visible; - logic issue, undefined; + logic issue, undefined, prefetch_abort; core_control_issue ctrl_issue ( diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv index 2d12c0a..038cd2b 100644 --- a/rtl/core/control/exception.sv +++ b/rtl/core/control/exception.sv @@ -8,6 +8,7 @@ module core_control_exception input ctrl_cycle next_cycle, input logic high_vectors, undefined, + prefetch_abort, mem_fault, output logic exception, @@ -20,7 +21,7 @@ module core_control_exception //TODO: irq, fiq, prefetch abort, swi - assign exception = undefined || mem_fault; + assign exception = undefined || prefetch_abort || mem_fault; assign exception_vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00}; always @(posedge clk or negedge rst_n) begin @@ -31,6 +32,9 @@ module core_control_exception end else if(mem_fault) begin vector_offset <= 3'b100; exception_mode <= `MODE_ABT; + end else if(prefetch_abort) begin + vector_offset <= 3'b011; + exception_mode <= `MODE_ABT; end else if(undefined) begin vector_offset <= 3'b001; exception_mode <= `MODE_UND; diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv index ffdf250..23ecdcf 100644 --- a/rtl/core/control/issue.sv +++ b/rtl/core/control/issue.sv @@ -8,6 +8,7 @@ module core_control_issue input insn_decode dec, input ptr insn_pc, + input logic issue_abort, input ctrl_cycle next_cycle, input logic next_bubble, @@ -18,6 +19,7 @@ module core_control_issue output logic issue, undefined, + prefetch_abort, output ptr pc, pc_visible, next_pc_visible @@ -34,12 +36,14 @@ module core_control_issue pc <= 0; undefined <= 0; pc_visible <= 2; + prefetch_abort <= 0; end else if(next_cycle.issue) begin if(valid) begin undefined <= dec.ctrl.undefined; + prefetch_abort <= issue_abort; `ifdef VERILATOR - if(dec.ctrl.undefined) + if(dec.ctrl.undefined && !issue_abort) $display("[core] undefined insn: [0x%08x] %08x", insn_pc << 2, insn); `endif end |