diff options
Diffstat (limited to 'rtl/core/control')
| -rw-r--r-- | rtl/core/control/control.sv | 6 | ||||
| -rw-r--r-- | rtl/core/control/debug.sv | 25 | ||||
| -rw-r--r-- | rtl/core/control/issue.sv | 2 |
3 files changed, 31 insertions, 2 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 92e27d6..7658ee9 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -5,6 +5,7 @@ module core_control input logic clk, rst_n, halt, + step, input insn_decode dec, input ptr insn_pc, @@ -156,4 +157,9 @@ module core_control .* ); + core_control_debug ctrl_dbg + ( + .* + ); + endmodule diff --git a/rtl/core/control/debug.sv b/rtl/core/control/debug.sv new file mode 100644 index 0000000..35b1334 --- /dev/null +++ b/rtl/core/control/debug.sv @@ -0,0 +1,25 @@ +`include "core/uarch.sv" + +module core_control_debug +( + input logic clk, + rst_n, + step, + + input ctrl_cycle next_cycle, + input logic issue, + next_bubble, + input insn_decode dec, + + output logic breakpoint +); + + logic stable, step_trigger; + + assign stable = next_cycle.issue && !dec.ctrl.nop && !next_bubble; + assign breakpoint = stable && (dec.ctrl.bkpt || step_trigger); + + always @(posedge clk or negedge rst_n) + step_trigger <= !rst_n ? 0 : step && (step_trigger || stable) && !breakpoint; + +endmodule diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv index b8cf3ff..ffdf250 100644 --- a/rtl/core/control/issue.sv +++ b/rtl/core/control/issue.sv @@ -18,7 +18,6 @@ module core_control_issue output logic issue, undefined, - breakpoint, output ptr pc, pc_visible, next_pc_visible @@ -28,7 +27,6 @@ module core_control_issue assign valid = !next_bubble && !halt; assign issue = next_cycle.issue && dec.ctrl.execute && valid; - assign breakpoint = issue && dec.ctrl.bkpt; assign next_pc_visible = insn_pc + 2; always_ff @(posedge clk or negedge rst_n) |