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-rw-r--r--rtl/core/control/control.sv (renamed from rtl/core/cycles.sv)5
-rw-r--r--rtl/core/control/ldst/pop.sv (renamed from rtl/core/cycles/ldst/pop.sv)2
2 files changed, 3 insertions, 4 deletions
diff --git a/rtl/core/cycles.sv b/rtl/core/control/control.sv
index ad35762..398c8c7 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/control/control.sv
@@ -1,6 +1,6 @@
`include "core/uarch.sv"
-module core_cycles
+module core_control
(
input logic clk,
dec_execute,
@@ -76,7 +76,7 @@ module core_cycles
((dec_update_flags || dec_conditional) && (final_update_flags || update_flags))
|| (final_writeback && (final_rd == dec_data.rn || final_rd == dec_snd.r));
- core_cycles_ldst_pop ldst_pop
+ core_control_ldst_pop ldst_pop
(
.regs(mem_regs),
.valid(pop_valid),
@@ -171,7 +171,6 @@ module core_cycles
data_imm <= dec_snd.imm;
data_shift_imm <= dec_snd.shift_imm;
- shifter.shl <= dec_snd.shl;
shifter.shr <= dec_snd.shr;
shifter.ror <= dec_snd.ror;
shifter.put_carry <= dec_snd.put_carry;
diff --git a/rtl/core/cycles/ldst/pop.sv b/rtl/core/control/ldst/pop.sv
index a4078d1..64dc04d 100644
--- a/rtl/core/cycles/ldst/pop.sv
+++ b/rtl/core/control/ldst/pop.sv
@@ -1,6 +1,6 @@
`include "core/uarch.sv"
-module core_cycles_ldst_pop
+module core_control_ldst_pop
(
input reg_list regs,