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Diffstat (limited to 'rtl/core/control/writeback.sv')
| -rw-r--r-- | rtl/core/control/writeback.sv | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 021d494..15b17ee 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -13,6 +13,7 @@ module core_control_writeback mem_data_rd, vector, q_alu, + input psr_flags alu_flags, input reg_num ra, popped, input logic pop_valid, @@ -26,10 +27,13 @@ module core_control_writeback final_writeback, update_flags, final_update_flags, - output word wr_value + output word wr_value, + output psr_flags wb_alu_flags ); - always @(posedge clk) begin + always_ff @(posedge clk) begin + wb_alu_flags <= alu_flags; + unique0 case(next_cycle) TRANSFER: if(mem_ready) @@ -128,6 +132,7 @@ module core_control_writeback final_update_flags = 0; wr_value = 0; + wb_alu_flags = {$bits(wb_alu_flags){1'b0}}; end endmodule |