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-rw-r--r--rtl/core/control/writeback.sv4
1 files changed, 3 insertions, 1 deletions
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index a7738fb..50e780d 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -10,6 +10,8 @@ module core_control_writeback
input word q_alu,
ldst_read,
input logic mem_ready,
+ mem_ex_fail,
+ mem_ex_lock,
mem_write,
input word mul_q_hi,
mul_q_lo,
@@ -62,7 +64,7 @@ module core_control_writeback
writeback = 0;
if(cycle.transfer)
- wr_value = ldst_read;
+ wr_value = (mem_ex_lock && mem_write) ? {31'd0, mem_ex_fail} : ldst_read;
else if(cycle.base_writeback)
wr_value = saved_base;
else if(cycle.mul || cycle.mul_hi_wb)