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-rw-r--r--rtl/core/control/mul.sv17
1 files changed, 8 insertions, 9 deletions
diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv
index c3625f8..5377045 100644
--- a/rtl/core/control/mul.sv
+++ b/rtl/core/control/mul.sv
@@ -36,15 +36,14 @@ module core_control_mul
mul_start <= 0;
unique case(next_cycle)
- ISSUE:
- if(issue) begin
- mul <= dec.mul;
- mul_add <= dec_mul.add;
- mul_long <= dec_mul.long_mul;
- mul_signed <= dec_mul.signed_mul;
- mul_r_add_hi <= dec_mul.r_add_hi;
- mul_r_add_lo <= dec_mul.r_add_lo;
- end
+ ISSUE: begin
+ mul <= issue && dec.mul;
+ mul_add <= dec_mul.add;
+ mul_long <= dec_mul.long_mul;
+ mul_signed <= dec_mul.signed_mul;
+ mul_r_add_hi <= dec_mul.r_add_hi;
+ mul_r_add_lo <= dec_mul.r_add_lo;
+ end
MUL:
mul_start <= cycle != MUL;