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-rw-r--r--rtl/core/control/cycles.sv4
1 files changed, 4 insertions, 0 deletions
diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv
index 5779990..772697d 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/control/cycles.sv
@@ -18,6 +18,7 @@ module core_control_cycles
mul_ready,
pop_valid,
trivial_shift,
+ ldst_reject,
ldst_writeback,
data_snd_shift_by_reg,
@@ -109,6 +110,9 @@ module core_control_cycles
if(mem_ready && mem_fault)
next_state = ESCALATE;
+
+ if(ldst_reject)
+ next_state = ISSUE;
end
MUL: