1 files changed, 59 insertions, 17 deletions

diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv
index 0c5d94c..5904a49 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/control/cycles.sv
@@ -22,50 +22,92 @@ module core_control_cycles
 	                  next_cycle
 );
 
+	/* qts-qii51007-recommended-hdl.pdf, p. 66
+	 * In Quartus II integrated synthesis, the enumerated type that defines the states for the
+	 * state machine must be of an unsigned integer type as in Example 13–52. If you do not
+	 * specify the enumerated type as int unsigned, a signed int type is used by default. In
+	 * this case, the Quartus II integrated synthesis synthesizes the design, but does not infer
+	 * or optimize the logic as a state machine.
+	 */
+	enum int unsigned
+	{
+		ISSUE,
+		RD_INDIRECT_SHIFT,
+		WITH_SHIFT,
+		TRANSFER,
+		BASE_WRITEBACK,
+		EXCEPTION,
+		MUL,
+		MUL_ACC_LD,
+		MUL_HI_WB
+	} state, next_state;
+
+	// TODO: debe estar escrito de tal forma que Quartus infiera una FSM
+
+	assign cycle.issue = state == ISSUE;
+	assign cycle.rd_indirect_shift = state == RD_INDIRECT_SHIFT;
+	assign cycle.with_shift = state == WITH_SHIFT;
+	assign cycle.transfer = state == TRANSFER;
+	assign cycle.base_writeback = state == BASE_WRITEBACK;
+	assign cycle.exception = state == EXCEPTION;
+	assign cycle.mul = state == MUL;
+	assign cycle.mul_acc_ld = state == MUL_ACC_LD;
+	assign cycle.mul_hi_wb = state == MUL_HI_WB;
+
+	assign next_cycle.issue = next_state == ISSUE;
+	assign next_cycle.rd_indirect_shift = next_state == RD_INDIRECT_SHIFT;
+	assign next_cycle.with_shift = next_state == WITH_SHIFT;
+	assign next_cycle.transfer = next_state == TRANSFER;
+	assign next_cycle.base_writeback = next_state == BASE_WRITEBACK;
+	assign next_cycle.exception = next_state == EXCEPTION;
+	assign next_cycle.mul = next_state == MUL;
+	assign next_cycle.mul_acc_ld = next_state == MUL_ACC_LD;
+	assign next_cycle.mul_hi_wb = next_state == MUL_HI_WB;
+
 	always_comb begin
-		next_cycle = ISSUE;
+		next_state = ISSUE;
 
-		unique case(cycle)
+		unique case(state)
 			ISSUE:
 				if(exception)
-					next_cycle = EXCEPTION;
+					next_state = EXCEPTION;
 				else if(halt)
-					next_cycle = ISSUE;
+					next_state = ISSUE;
 				else if(mul)
-					next_cycle = mul_add ? MUL_ACC_LD : MUL;
+					next_state = mul_add ? MUL_ACC_LD : MUL;
 				else if(data_snd_shift_by_reg)
-					next_cycle = RD_INDIRECT_SHIFT;
+					next_state = RD_INDIRECT_SHIFT;
 				else if(!trivial_shift)
-					next_cycle = WITH_SHIFT;
+					next_state = WITH_SHIFT;
 
 			RD_INDIRECT_SHIFT:
 				if(!trivial_shift)
-					next_cycle = WITH_SHIFT;
+					next_state = WITH_SHIFT;
 
 			TRANSFER:
 				if(!mem_ready || pop_valid)
-					next_cycle = TRANSFER;
+					next_state = TRANSFER;
 				else if(ldst_writeback)
-					next_cycle = BASE_WRITEBACK;
+					next_state = BASE_WRITEBACK;
 
 			MUL:
 				if(!mul_ready)
-					next_cycle = MUL;
+					next_state = MUL;
 				else if(mul_long)
-					next_cycle = MUL_HI_WB;
+					next_state = MUL_HI_WB;
 
 			MUL_ACC_LD:
-				next_cycle = MUL;
+				next_state = MUL;
 		endcase
 
 		if(bubble)
-			next_cycle = ISSUE;
-		else if(next_cycle == ISSUE && ldst) begin
-			next_cycle = TRANSFER;
+			next_state = ISSUE;
+		else if(next_state == ISSUE && ldst) begin
+			next_state = TRANSFER;
 		end
 	end
 
 	always_ff @(posedge clk or negedge rst_n)
-		cycle <= !rst_n ? ISSUE : next_cycle;
+		state <= !rst_n ? ISSUE : next_state;
 
 endmodule