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Diffstat (limited to '')
| -rw-r--r-- | rtl/core/control/cycles.sv | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv index 0a70d5e..0c5d94c 100644 --- a/rtl/core/control/cycles.sv +++ b/rtl/core/control/cycles.sv @@ -4,6 +4,7 @@ module core_control_cycles ( input logic clk, rst_n, + halt, mul, ldst, bubble, @@ -28,6 +29,8 @@ module core_control_cycles ISSUE: if(exception) next_cycle = EXCEPTION; + else if(halt) + next_cycle = ISSUE; else if(mul) next_cycle = mul_add ? MUL_ACC_LD : MUL; else if(data_snd_shift_by_reg) |