diff options
Diffstat (limited to 'rtl/cache/cache_control.sv')
| -rw-r--r-- | rtl/cache/cache_control.sv | 152 |
1 files changed, 85 insertions, 67 deletions
diff --git a/rtl/cache/cache_control.sv b/rtl/cache/cache_control.sv index fb7896a..33d380a 100644 --- a/rtl/cache/cache_control.sv +++ b/rtl/cache/cache_control.sv @@ -3,51 +3,60 @@ module cache_control #(parameter TOKEN_AT_RESET=0) ( - input logic clk, - rst_n, + input logic clk, + rst_n, - input addr_tag core_tag, - input addr_index core_index, - input logic core_read, - core_write, - core_lock, - input line core_data_wr, - output logic core_waitrequest, - output logic[1:0] core_response, + input addr_tag core_tag, + input addr_index core_index, + input logic core_read, + core_write, + core_lock, + input line core_data_wr, + output logic core_waitrequest, - input ring_req in_data, - input logic in_data_valid, - output logic in_data_ready, + input ring_req in_data, + input logic in_data_valid, + output logic in_data_ready, - input logic out_data_ready, - output ring_req out_data, - output logic out_data_valid, + input logic out_data_ready, + output ring_req out_data, + output logic out_data_valid, - input ring_token in_token, - input logic in_token_valid, + input ring_token in_token, + input logic in_token_valid, - output ring_token out_token, - output logic out_token_valid, + output ring_token out_token, + output logic out_token_valid, // Señales para la SRAM - input addr_tag tag_rd, - input line data_rd, - input line_state state_rd, - - output addr_index index_rd, - index_wr, - output logic write_data, - write_state, - output addr_tag tag_wr, - output line data_wr, - output line_state state_wr, - - input logic mem_waitrequest, - input line mem_readdata, - output word mem_address, - output logic mem_read, - mem_write, - output line mem_writedata + input addr_tag tag_rd, + input line data_rd, + input line_state state_rd, + + input line monitor_update, + input logic monitor_commit, + output logic monitor_acquire, + monitor_fail, + monitor_release, + + output addr_index index_rd, + index_wr, + output logic write_data, + write_state, + output addr_tag tag_wr, + output line data_wr, + output line_state state_wr, + + input logic mem_waitrequest, + input line mem_readdata, + output word mem_address, + output logic mem_read, + mem_write, + output line mem_writedata, + + input logic dbg_write, + input addr_index debug_index, + output logic debug_ready ); enum int unsigned @@ -58,24 +67,15 @@ module cache_control REPLY } state, next_state; - logic accept_snoop, end_reply, in_hold_valid, last_hop, lock_line, locked, - may_send, may_send_if_token_held, mem_begin, mem_end, mem_read_end, mem_wait, - monitor_acquire, monitor_commit, monitor_fail, out_stall, wait_reply, replace, - retry, send, send_inval, send_read, snoop_hit, set_reply, unlock_line, writeback; + logic accept_snoop, debug, end_reply, in_hold_valid, last_hop, lock_line, + locked, may_send, may_send_if_token_held, mem_begin, mem_end, mem_read_end, + mem_wait, out_stall, wait_reply, replace, retry, send, send_inval, + send_read, snoop_hit, set_reply, unlock_line, writeback; ring_req in_hold, send_data, fwd_data, stall_data, out_data_next; - line monitor_data_rd, monitor_data_wr; - addr_tag mem_tag, monitor_tag; - addr_index mem_index, monitor_index; - - /* Avalon p. 15: - * - 00: OKAY - Successful response for a transaction. - * - 10: SLVERR - Error from an endpoint agent. Indicates an unsuccessful transaction. - */ - assign core_response = {monitor_fail, 1'b0}; - assign monitor_commit = !core_lock || (monitor_tag == core_tag && monitor_index == core_index - && monitor_data_rd == data_rd); + addr_tag mem_tag; + addr_index mem_index; assign mem_end = (mem_read || mem_write) && !mem_waitrequest; assign mem_wait = (mem_read || mem_write) && mem_waitrequest; @@ -135,6 +135,7 @@ module cache_control monitor_fail = 0; monitor_acquire = 0; + monitor_release = 0; core_waitrequest = 1; in_data_ready = !in_hold_valid; @@ -146,17 +147,19 @@ module cache_control end_reply = in_hold_valid; // Se termina el paso de ese mensaje in_data_ready = 1; end + // Si no es el último salto y hay reply - if (!last_hop && in_hold.reply) + if (!last_hop && in_hold.reply && !in_hold.inval) in_data_ready = 1; if (accept_snoop) index_rd = in_hold.index; + + if (debug) + index_rd = debug_index; end CORE: begin - monitor_acquire = core_read && core_lock; - if (replace) begin state_wr = INVALID; write_state = 1; @@ -175,8 +178,10 @@ module cache_control send_inval = 1; end - {SHARED, 1'b0}: + {SHARED, 1'b0}: begin + monitor_acquire = core_lock; core_waitrequest = 0; + end {SHARED, 1'b1}: begin /* No hacemos write_data ya que reintentaremos el @@ -192,8 +197,10 @@ module cache_control send_inval = 1; end - {EXCLUSIVE, 1'b0}: + {EXCLUSIVE, 1'b0}: begin + monitor_acquire = core_lock; core_waitrequest = 0; + end {EXCLUSIVE, 1'b1}: begin state_wr = MODIFIED; @@ -201,19 +208,28 @@ module cache_control write_state = monitor_commit; monitor_fail = !monitor_commit; + monitor_release = core_lock; + core_waitrequest = 0; end - {MODIFIED, 1'b0}: + {MODIFIED, 1'b0}: begin + monitor_acquire = core_lock; core_waitrequest = 0; + end {MODIFIED, 1'b1}: begin write_data = monitor_commit; monitor_fail = !monitor_commit; + monitor_release = core_lock; + core_waitrequest = 0; end endcase + + if (monitor_release) + data_wr = monitor_update; end SNOOP: begin @@ -286,6 +302,9 @@ module cache_control write_data = 0; write_state = 0; + monitor_acquire = 0; + monitor_release = 0; + in_data_ready = !in_hold_valid; core_waitrequest = 1; end @@ -314,6 +333,7 @@ module cache_control end always_comb begin + debug = 0; next_state = ACCEPT; unique case (state) @@ -322,6 +342,8 @@ module cache_control next_state = SNOOP; else if (in_hold_valid && last_hop && in_hold.read) next_state = REPLY; + else if (dbg_write && !debug_ready) + debug = 1; else if ((core_read || core_write) && !wait_reply && (!locked || may_send)) next_state = CORE; @@ -349,6 +371,8 @@ module cache_control mem_read <= 0; mem_write <= 0; + + debug_ready <= 0; end else begin out_token.e0.tag <= core_tag; out_token.e0.index <= core_index; @@ -384,6 +408,8 @@ module cache_control mem_read <= !writeback; mem_write <= writeback; end + + debug_ready <= debug; end always_ff @(posedge clk) begin @@ -398,14 +424,6 @@ module cache_control mem_index <= index_wr; mem_writedata <= data_rd; end - - if (monitor_acquire && !core_waitrequest) begin - monitor_tag <= core_tag; - monitor_index <= core_index; - - monitor_data_rd <= data_rd; - monitor_data_wr <= data_rd; - end end endmodule |