diff options
Diffstat (limited to 'cache_hw.tcl')
| -rw-r--r-- | cache_hw.tcl | 48 |
1 files changed, 44 insertions, 4 deletions
diff --git a/cache_hw.tcl b/cache_hw.tcl index 4a06546..93c8748 100644 --- a/cache_hw.tcl +++ b/cache_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Mon Oct 02 07:43:58 GMT 2023 +# Wed Oct 04 21:42:03 GMT 2023 # DO NOT MODIFY # -# cache "8KiB 1-way cache w/ controller" v1.0 -# 2023.10.02.07:43:58 +# cache "64KiB 1-way cache w/ controller" v1.0 +# 2023.10.04.21:42:03 # # @@ -24,7 +24,7 @@ set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property AUTHOR "" -set_module_property DISPLAY_NAME "8KiB 1-way cache w/ controller" +set_module_property DISPLAY_NAME "64KiB 1-way cache w/ controller" set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property REPORT_TO_TALKBACK false @@ -45,6 +45,8 @@ add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv add_fileset_file sram.sv SYSTEM_VERILOG PATH rtl/cache/sram.sv +add_fileset_file monitor.sv SYSTEM_VERILOG PATH rtl/cache/monitor.sv +add_fileset_file cache_debug.sv SYSTEM_VERILOG PATH rtl/cache/cache_debug.sv # @@ -256,3 +258,41 @@ add_interface_port mem mem_readdata readdata Input 128 add_interface_port mem mem_writedata writedata Output 128 add_interface_port mem mem_waitrequest waitrequest Input 1 + +# +# connection point dbg +# +add_interface dbg avalon end +set_interface_property dbg addressUnits WORDS +set_interface_property dbg associatedClock clock_sink +set_interface_property dbg associatedReset reset_sink +set_interface_property dbg bitsPerSymbol 8 +set_interface_property dbg burstOnBurstBoundariesOnly false +set_interface_property dbg burstcountUnits WORDS +set_interface_property dbg explicitAddressSpan 0 +set_interface_property dbg holdTime 0 +set_interface_property dbg linewrapBursts false +set_interface_property dbg maximumPendingReadTransactions 0 +set_interface_property dbg maximumPendingWriteTransactions 0 +set_interface_property dbg readLatency 0 +set_interface_property dbg readWaitTime 1 +set_interface_property dbg setupTime 0 +set_interface_property dbg timingUnits Cycles +set_interface_property dbg writeWaitTime 0 +set_interface_property dbg ENABLED true +set_interface_property dbg EXPORT_OF "" +set_interface_property dbg PORT_NAME_MAP "" +set_interface_property dbg CMSIS_SVD_VARIABLES "" +set_interface_property dbg SVD_ADDRESS_GROUP "" + +add_interface_port dbg dbg_read read Input 1 +add_interface_port dbg dbg_write write Input 1 +add_interface_port dbg dbg_address address Input 3 +add_interface_port dbg dbg_readdata readdata Output 32 +add_interface_port dbg dbg_waitrequest waitrequest Output 1 +add_interface_port dbg dbg_writedata writedata Input 32 +set_interface_assignment dbg embeddedsw.configuration.isFlash 0 +set_interface_assignment dbg embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment dbg embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment dbg embeddedsw.configuration.isPrintableDevice 0 + |