summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--platform/wavelet3d/host_sw/cross-riscv32-none-elf.txt2
-rw-r--r--platform/wavelet3d/w3d_interconnect.sv42
-rw-r--r--platform/wavelet3d/w3d_top.sv4
-rw-r--r--rtl/gfx/gfx_top.sv13
-rw-r--r--rtl/gfx/gfx_xbar_vram.sv198
5 files changed, 251 insertions, 8 deletions
diff --git a/platform/wavelet3d/host_sw/cross-riscv32-none-elf.txt b/platform/wavelet3d/host_sw/cross-riscv32-none-elf.txt
index 747bcac..920b932 100644
--- a/platform/wavelet3d/host_sw/cross-riscv32-none-elf.txt
+++ b/platform/wavelet3d/host_sw/cross-riscv32-none-elf.txt
@@ -22,4 +22,4 @@ skip_sanity_check = true
default_flash_addr = '0x00000000'
default_flash_size = '0x04000000'
default_ram_addr = '0x04000000'
-default_ram_size = '0x1c000000'
+default_ram_size = '0x18000000'
diff --git a/platform/wavelet3d/w3d_interconnect.sv b/platform/wavelet3d/w3d_interconnect.sv
index 7456212..17d7522 100644
--- a/platform/wavelet3d/w3d_interconnect.sv
+++ b/platform/wavelet3d/w3d_interconnect.sv
@@ -3,11 +3,12 @@ module w3d_interconnect
input logic clk,
srst_n,
- if_axib.m dram,
-
- if_axib.s host_dbus,
+ if_axib.s gfx_vram,
+ host_dbus,
host_ibus,
+ if_axib.m dram,
+
if_axil.m gfx_ctrl,
external_io
);
@@ -20,6 +21,7 @@ module w3d_interconnect
.clk,
.srst_n,
.dram,
+ .gfx_vram,
.host_dbus(dram_host.s),
.host_ibus
);
@@ -49,13 +51,14 @@ module w3d_interconnect_dram
input logic clk,
srst_n,
- if_axib.s host_dbus,
+ if_axib.s gfx_vram,
+ host_dbus,
host_ibus,
if_axib.m dram
);
- defparam xbar.NM = 2;
+ defparam xbar.NM = 3;
defparam xbar.NS = 1;
defparam xbar.OPT_LOWPOWER = 0;
@@ -70,30 +73,37 @@ module w3d_interconnect_dram
.S_AXI_ARESETN(srst_n),
.S_AXI_AWVALID({
+ gfx_vram.awvalid,
host_dbus.awvalid,
host_ibus.awvalid
}),
.S_AXI_AWREADY({
+ gfx_vram.awready,
host_dbus.awready,
host_ibus.awready
}),
.S_AXI_AWID({
+ gfx_vram.awid,
host_dbus.awid,
host_ibus.awid
}),
.S_AXI_AWADDR({
+ gfx_vram.awaddr,
host_dbus.awaddr,
host_ibus.awaddr
}),
.S_AXI_AWLEN({
+ gfx_vram.awlen,
host_dbus.awlen,
host_ibus.awlen
}),
.S_AXI_AWSIZE({
+ gfx_vram.awsize,
host_dbus.awsize,
host_ibus.awsize
}),
.S_AXI_AWBURST({
+ gfx_vram.awburst,
host_dbus.awburst,
host_ibus.awburst
}),
@@ -103,68 +113,84 @@ module w3d_interconnect_dram
.S_AXI_AWQOS('0),
.S_AXI_WVALID({
+ gfx_vram.wvalid,
host_dbus.wvalid,
host_ibus.wvalid
}),
.S_AXI_WREADY({
+ gfx_vram.wready,
host_dbus.wready,
host_ibus.wready
}),
.S_AXI_WDATA({
+ gfx_vram.wdata,
host_dbus.wdata,
host_ibus.wdata
}),
.S_AXI_WSTRB({
+ gfx_vram.wstrb,
host_dbus.wstrb,
host_ibus.wstrb
}),
.S_AXI_WLAST({
+ gfx_vram.wlast,
host_dbus.wlast,
host_ibus.wlast
}),
.S_AXI_BVALID({
+ gfx_vram.bvalid,
host_dbus.bvalid,
host_ibus.bvalid
}),
.S_AXI_BREADY({
+ gfx_vram.bready,
host_dbus.bready,
host_ibus.bready
}),
.S_AXI_BID({
+ gfx_vram.bid,
host_dbus.bid,
host_ibus.bid
}),
.S_AXI_BRESP({
+ gfx_vram.bresp,
host_dbus.bresp,
host_ibus.bresp
}),
.S_AXI_ARVALID({
+ gfx_vram.arvalid,
host_dbus.arvalid,
host_ibus.arvalid
}),
.S_AXI_ARREADY({
+ gfx_vram.arready,
host_dbus.arready,
host_ibus.arready
}),
.S_AXI_ARID({
+ gfx_vram.arid,
host_dbus.arid,
host_ibus.arid
}),
.S_AXI_ARADDR({
+ gfx_vram.araddr,
host_dbus.araddr,
host_ibus.araddr
}),
.S_AXI_ARLEN({
+ gfx_vram.arlen,
host_dbus.arlen,
host_ibus.arlen
}),
.S_AXI_ARSIZE({
+ gfx_vram.arsize,
host_dbus.arsize,
host_ibus.arsize
}),
.S_AXI_ARBURST({
+ gfx_vram.arburst,
host_dbus.arburst,
host_ibus.arburst
}),
@@ -174,26 +200,32 @@ module w3d_interconnect_dram
.S_AXI_ARQOS('0),
.S_AXI_RVALID({
+ gfx_vram.rvalid,
host_dbus.rvalid,
host_ibus.rvalid
}),
.S_AXI_RREADY({
+ gfx_vram.rready,
host_dbus.rready,
host_ibus.rready
}),
.S_AXI_RID({
+ gfx_vram.rid,
host_dbus.rid,
host_ibus.rid
}),
.S_AXI_RDATA({
+ gfx_vram.rdata,
host_dbus.rdata,
host_ibus.rdata
}),
.S_AXI_RRESP({
+ gfx_vram.rresp,
host_dbus.rresp,
host_ibus.rresp
}),
.S_AXI_RLAST({
+ gfx_vram.rlast,
host_dbus.rlast,
host_ibus.rlast
}),
diff --git a/platform/wavelet3d/w3d_top.sv b/platform/wavelet3d/w3d_top.sv
index b80446a..b4d903e 100644
--- a/platform/wavelet3d/w3d_top.sv
+++ b/platform/wavelet3d/w3d_top.sv
@@ -64,7 +64,7 @@ module w3d_top
);
if_tap host_jtag();
- if_axib dram(), host_dbus(), host_ibus();
+ if_axib dram(), host_dbus(), host_ibus(), gfx_vram();
if_axil mmio(), gfx_ctrl();
assign dram_awid = dram.s.awid;
@@ -137,6 +137,7 @@ module w3d_top
.clk,
.rst_n,
.srst_n,
+ .vram(gfx_vram.m),
.host_ctrl(gfx_ctrl.s)
);
@@ -155,6 +156,7 @@ module w3d_top
.srst_n,
.dram(dram.m),
.gfx_ctrl(gfx_ctrl.m),
+ .gfx_vram(gfx_vram.s),
.host_dbus(host_dbus.s),
.host_ibus(host_ibus.s),
.external_io(mmio.m)
diff --git a/rtl/gfx/gfx_top.sv b/rtl/gfx/gfx_top.sv
index 8b2506b..99f2133 100644
--- a/rtl/gfx/gfx_top.sv
+++ b/rtl/gfx/gfx_top.sv
@@ -5,6 +5,8 @@ import gfx::*;
rst_n,
srst_n,
+ if_axib.m vram,
+
if_axil.s host_ctrl
);
@@ -55,7 +57,7 @@ import gfx::*;
.insn_mem(insn_mem.m)
);
- gfx_xbar_sched xbar
+ gfx_xbar_sched sched_xbar
(
.clk,
.srst_n,
@@ -68,6 +70,15 @@ import gfx::*;
.host_ctrl(host_ctrl_axi.m)
);
+ gfx_xbar_vram vram_xbar
+ (
+ .clk,
+ .srst_n,
+ .vram,
+ .shader_0_data(data_mem.s),
+ .shader_0_insn(insn_mem.s)
+ );
+
/*TODO
gfx_raster raster
(
diff --git a/rtl/gfx/gfx_xbar_vram.sv b/rtl/gfx/gfx_xbar_vram.sv
new file mode 100644
index 0000000..3ce8425
--- /dev/null
+++ b/rtl/gfx/gfx_xbar_vram.sv
@@ -0,0 +1,198 @@
+module gfx_xbar_vram
+(
+ input logic clk,
+ srst_n,
+
+ if_axib.s shader_0_data,
+ shader_0_insn,
+
+ if_axib.m vram
+);
+
+ defparam xbar.NM = 2;
+ defparam xbar.NS = 1;
+ defparam xbar.OPT_LOWPOWER = 0;
+
+ defparam
+ xbar.SLAVE_ADDR = '0,
+ xbar.SLAVE_MASK = '0,
+ xbar.C_AXI_ID_WIDTH = 8;
+
+ axixbar xbar
+ (
+ .S_AXI_ACLK(clk),
+ .S_AXI_ARESETN(srst_n),
+
+ .S_AXI_AWVALID({
+ shader_0_data.awvalid,
+ shader_0_insn.awvalid
+ }),
+ .S_AXI_AWREADY({
+ shader_0_data.awready,
+ shader_0_insn.awready
+ }),
+ .S_AXI_AWID({
+ shader_0_data.awid,
+ shader_0_insn.awid
+ }),
+ .S_AXI_AWADDR({
+ shader_0_data.awaddr,
+ shader_0_insn.awaddr
+ }),
+ .S_AXI_AWLEN({
+ shader_0_data.awlen,
+ shader_0_insn.awlen
+ }),
+ .S_AXI_AWSIZE({
+ shader_0_data.awsize,
+ shader_0_insn.awsize
+ }),
+ .S_AXI_AWBURST({
+ shader_0_data.awburst,
+ shader_0_insn.awburst
+ }),
+ .S_AXI_AWLOCK('0),
+ .S_AXI_AWCACHE('0),
+ .S_AXI_AWPROT('0),
+ .S_AXI_AWQOS('0),
+
+ .S_AXI_WVALID({
+ shader_0_data.wvalid,
+ shader_0_insn.wvalid
+ }),
+ .S_AXI_WREADY({
+ shader_0_data.wready,
+ shader_0_insn.wready
+ }),
+ .S_AXI_WDATA({
+ shader_0_data.wdata,
+ shader_0_insn.wdata
+ }),
+ .S_AXI_WSTRB({
+ shader_0_data.wstrb,
+ shader_0_insn.wstrb
+ }),
+ .S_AXI_WLAST({
+ shader_0_data.wlast,
+ shader_0_insn.wlast
+ }),
+
+ .S_AXI_BVALID({
+ shader_0_data.bvalid,
+ shader_0_insn.bvalid
+ }),
+ .S_AXI_BREADY({
+ shader_0_data.bready,
+ shader_0_insn.bready
+ }),
+ .S_AXI_BID({
+ shader_0_data.bid,
+ shader_0_insn.bid
+ }),
+ .S_AXI_BRESP({
+ shader_0_data.bresp,
+ shader_0_insn.bresp
+ }),
+
+ .S_AXI_ARVALID({
+ shader_0_data.arvalid,
+ shader_0_insn.arvalid
+ }),
+ .S_AXI_ARREADY({
+ shader_0_data.arready,
+ shader_0_insn.arready
+ }),
+ .S_AXI_ARID({
+ shader_0_data.arid,
+ shader_0_insn.arid
+ }),
+ .S_AXI_ARADDR({
+ shader_0_data.araddr,
+ shader_0_insn.araddr
+ }),
+ .S_AXI_ARLEN({
+ shader_0_data.arlen,
+ shader_0_insn.arlen
+ }),
+ .S_AXI_ARSIZE({
+ shader_0_data.arsize,
+ shader_0_insn.arsize
+ }),
+ .S_AXI_ARBURST({
+ shader_0_data.arburst,
+ shader_0_insn.arburst
+ }),
+ .S_AXI_ARLOCK('0),
+ .S_AXI_ARCACHE('0),
+ .S_AXI_ARPROT('0),
+ .S_AXI_ARQOS('0),
+
+ .S_AXI_RVALID({
+ shader_0_data.rvalid,
+ shader_0_insn.rvalid
+ }),
+ .S_AXI_RREADY({
+ shader_0_data.rready,
+ shader_0_insn.rready
+ }),
+ .S_AXI_RID({
+ shader_0_data.rid,
+ shader_0_insn.rid
+ }),
+ .S_AXI_RDATA({
+ shader_0_data.rdata,
+ shader_0_insn.rdata
+ }),
+ .S_AXI_RRESP({
+ shader_0_data.rresp,
+ shader_0_insn.rresp
+ }),
+ .S_AXI_RLAST({
+ shader_0_data.rlast,
+ shader_0_insn.rlast
+ }),
+
+ .M_AXI_AWVALID(vram.awvalid),
+ .M_AXI_AWREADY(vram.awready),
+ .M_AXI_AWID(vram.awid),
+ .M_AXI_AWADDR(vram.awaddr),
+ .M_AXI_AWLEN(vram.awlen),
+ .M_AXI_AWSIZE(vram.awsize),
+ .M_AXI_AWBURST(vram.awburst),
+ .M_AXI_AWLOCK(),
+ .M_AXI_AWCACHE(),
+ .M_AXI_AWPROT(),
+ .M_AXI_AWQOS(),
+
+ .M_AXI_WVALID(vram.wvalid),
+ .M_AXI_WREADY(vram.wready),
+ .M_AXI_WDATA(vram.wdata),
+ .M_AXI_WSTRB(vram.wstrb),
+ .M_AXI_WLAST(vram.wlast),
+
+ .M_AXI_BVALID(vram.bvalid),
+ .M_AXI_BREADY(vram.bready),
+ .M_AXI_BID(vram.bid),
+ .M_AXI_BRESP(vram.bresp),
+
+ .M_AXI_ARVALID(vram.arvalid),
+ .M_AXI_ARREADY(vram.arready),
+ .M_AXI_ARID(vram.arid),
+ .M_AXI_ARADDR(vram.araddr),
+ .M_AXI_ARLEN(vram.arlen),
+ .M_AXI_ARSIZE(vram.arsize),
+ .M_AXI_ARBURST(vram.arburst),
+ .M_AXI_ARLOCK(),
+ .M_AXI_ARCACHE(),
+ .M_AXI_ARPROT(),
+ .M_AXI_ARQOS(),
+
+ .M_AXI_RVALID(vram.rvalid),
+ .M_AXI_RREADY(vram.rready),
+ .M_AXI_RID(vram.rid),
+ .M_AXI_RDATA(vram.rdata),
+ .M_AXI_RRESP(vram.rresp),
+ .M_AXI_RLAST(vram.rlast)
+ );
+
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 05:28:29 +0000