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-rw-r--r--rtl/gfx/gfx.sv48
-rw-r--r--rtl/gfx/gfx_defs.sv6
-rw-r--r--rtl/gfx/gfx_mem.sv56
-rw-r--r--rtl/gfx/gfx_rop.sv4
-rw-r--r--rtl/gfx/gfx_scanout.sv6
-rw-r--r--rtl/gfx/gfx_scanout_dac.sv48
-rw-r--r--rtl/top/test_fb.sv40
7 files changed, 107 insertions, 101 deletions
diff --git a/rtl/gfx/gfx.sv b/rtl/gfx/gfx.sv
index fef08a7..c25182c 100644
--- a/rtl/gfx/gfx.sv
+++ b/rtl/gfx/gfx.sv
@@ -2,28 +2,28 @@
module gfx
(
- input logic clk,
- rst_n,
-
- input logic[5:0] cmd_address,
- input logic cmd_read,
- cmd_write,
- input logic[31:0] cmd_writedata,
- output logic[31:0] cmd_readdata,
-
- input logic mem_waitrequest,
- mem_readdatavalid,
- input mem_word mem_readdata,
- output mem_addr mem_address,
- output logic mem_read,
- mem_write,
- output mem_word mem_writedata,
-
- input logic scan_ready,
- output logic scan_valid,
- scan_endofpacket,
- scan_startofpacket,
- output rgb30 scan_data
+ input logic clk,
+ rst_n,
+
+ input logic[5:0] cmd_address,
+ input logic cmd_read,
+ cmd_write,
+ input logic[31:0] cmd_writedata,
+ output logic[31:0] cmd_readdata,
+
+ input logic mem_waitrequest,
+ mem_readdatavalid,
+ input vram_word mem_readdata,
+ output vram_byte_addr mem_address,
+ output logic mem_read,
+ mem_write,
+ output vram_word mem_writedata,
+
+ input logic scan_ready,
+ output logic scan_valid,
+ scan_endofpacket,
+ scan_startofpacket,
+ output rgb30 scan_data
);
logic enable_clear, start_clear, swap_buffers;
@@ -101,7 +101,7 @@ module gfx
);
logic rop_mask_assert, rop_ready, rop_write;
- mem_word rop_writedata;
+ vram_word rop_writedata;
half_coord rop_address;
linear_coord rop_mask_addr;
@@ -116,7 +116,7 @@ module gfx
);
logic fb_readdatavalid, fb_waitrequest, rop_waitrequest;
- mem_word fb_readdata;
+ vram_word fb_readdata;
gfx_mem mem
(
diff --git a/rtl/gfx/gfx_defs.sv b/rtl/gfx/gfx_defs.sv
index dc5f5c4..cbe9f1c 100644
--- a/rtl/gfx/gfx_defs.sv
+++ b/rtl/gfx/gfx_defs.sv
@@ -164,8 +164,8 @@ typedef struct packed
`define GFX_MEM_FIFO_DEPTH 4 // Ajustar
`define GFX_MEM_TRANS_DEPTH 4 // Ajustar
-typedef logic[`GFX_MEM_DATA_BITS - 1:0] mem_word;
-typedef logic[`GFX_MEM_ADDR_BITS - 1:0] mem_addr;
-typedef logic[`GFX_MEM_WORD_ADDR_BITS - 1:0] mem_word_addr;
+typedef logic[`GFX_MEM_DATA_BITS - 1:0] vram_word;
+typedef logic[`GFX_MEM_ADDR_BITS - 1:0] vram_byte_addr;
+typedef logic[`GFX_MEM_WORD_ADDR_BITS - 1:0] vram_addr;
`endif
diff --git a/rtl/gfx/gfx_mem.sv b/rtl/gfx/gfx_mem.sv
index a4cf240..9e522f4 100644
--- a/rtl/gfx/gfx_mem.sv
+++ b/rtl/gfx/gfx_mem.sv
@@ -2,27 +2,27 @@
module gfx_mem
(
- input logic clk,
- rst_n,
-
- input logic mem_waitrequest,
- mem_readdatavalid,
- input mem_word mem_readdata,
- output mem_addr mem_address,
- output logic mem_read,
- mem_write,
- output mem_word mem_writedata,
-
- input logic rop_write,
- input mem_word rop_writedata,
- input half_coord rop_address,
- output logic rop_waitrequest,
-
- input logic fb_read,
- input half_coord fb_address,
- output logic fb_waitrequest,
- fb_readdatavalid,
- output mem_word fb_readdata
+ input logic clk,
+ rst_n,
+
+ input logic mem_waitrequest,
+ mem_readdatavalid,
+ input vram_word mem_readdata,
+ output vram_byte_addr mem_address,
+ output logic mem_read,
+ mem_write,
+ output vram_word mem_writedata,
+
+ input logic rop_write,
+ input vram_word rop_writedata,
+ input half_coord rop_address,
+ output logic rop_waitrequest,
+
+ input logic fb_read,
+ input half_coord fb_address,
+ output logic fb_waitrequest,
+ fb_readdatavalid,
+ output vram_word fb_readdata
);
// Esto está mal, hay que reescribirlo totalmente
@@ -31,9 +31,9 @@ module gfx_mem
struct packed
{
- mem_addr address;
- logic write;
- mem_word writedata;
+ vram_addr address;
+ logic write;
+ vram_word writedata;
} trans_in, trans_out, trans_in_skid, trans_out_skid;
/* Cerrar timing aquí no es tan fácil, debido al enrutamiento al el que
@@ -85,7 +85,7 @@ module gfx_mem
.*
);
- gfx_pipes #(.WIDTH($bits(mem_word)), .DEPTH(`GFX_MEM_FIFO_DEPTH)) readdata_pipes
+ gfx_pipes #(.WIDTH($bits(vram_word)), .DEPTH(`GFX_MEM_FIFO_DEPTH)) readdata_pipes
(
.in(mem_readdata),
.out(fb_readdata),
@@ -105,7 +105,7 @@ module gfx_mem
assign mem_read = mem_rw && !trans_out_skid.write;
assign mem_write = mem_rw && trans_out_skid.write;
- assign mem_address = trans_out_skid.address;
+ assign mem_address = {trans_out_skid.address, {`GFX_MEM_SUBWORD_BITS{1'b0}}};
assign mem_writedata = trans_out_skid.writedata;
always_comb begin
@@ -117,11 +117,11 @@ module gfx_mem
if (fb_read) begin
fb_waitrequest = !in_ready;
trans_in.write = 0;
- trans_in.address = {6'd0, fb_address};
+ trans_in.address = {5'd0, fb_address};
end else begin
rop_waitrequest = !in_ready;
trans_in.write = 1;
- trans_in.address = {6'd0, rop_address};
+ trans_in.address = {5'd0, rop_address};
end
end
diff --git a/rtl/gfx/gfx_rop.sv b/rtl/gfx/gfx_rop.sv
index c0e3bf1..dcdafe0 100644
--- a/rtl/gfx/gfx_rop.sv
+++ b/rtl/gfx/gfx_rop.sv
@@ -11,7 +11,7 @@ module gfx_rop
input logic rop_waitrequest,
output logic rop_write,
- output mem_word rop_writedata,
+ output vram_word rop_writedata,
output half_coord rop_address,
output linear_coord mask_addr,
@@ -26,7 +26,7 @@ module gfx_rop
} state;
logic hi;
- mem_word color_hi, color_lo;
+ vram_word color_hi, color_lo;
frag_paint hold;
assign {color_hi, color_lo} = hold.color;
diff --git a/rtl/gfx/gfx_scanout.sv b/rtl/gfx/gfx_scanout.sv
index a7aa71a..1d738c4 100644
--- a/rtl/gfx/gfx_scanout.sv
+++ b/rtl/gfx/gfx_scanout.sv
@@ -13,7 +13,7 @@ module gfx_scanout
input logic fb_waitrequest,
fb_readdatavalid,
- input mem_word fb_readdata,
+ input vram_word fb_readdata,
output logic fb_read,
output half_coord fb_address,
@@ -30,7 +30,7 @@ module gfx_scanout
fb_ready, mask_fifo_ready, fb_fifo_valid, mask_fifo_valid,
pop, put, put_mask, next_vsync, start_vsync, wait_vsync;
- mem_word fb_fifo_out;
+ vram_word fb_fifo_out;
half_coord commit_addr, mask_in_addr, mask_out_addr, mask_hold_addr, max_addr;
assign mask_addr = mask_in_addr[$bits(mask_in_addr) - 1:$bits(mask_in_addr) - $bits(mask_addr)];
@@ -78,7 +78,7 @@ module gfx_scanout
);
// 2x para evitar potencial overflow cuando fb_read=1 pero mask_fifo está llena
- gfx_fifo #(.WIDTH($bits(mem_word)), .DEPTH(2 * `GFX_SCANOUT_FIFO_DEPTH)) fb_fifo
+ gfx_fifo #(.WIDTH($bits(vram_word)), .DEPTH(2 * `GFX_SCANOUT_FIFO_DEPTH)) fb_fifo
(
.in(fb_readdata),
.out(fb_fifo_out),
diff --git a/rtl/gfx/gfx_scanout_dac.sv b/rtl/gfx/gfx_scanout_dac.sv
index ba8b0b7..c199d78 100644
--- a/rtl/gfx/gfx_scanout_dac.sv
+++ b/rtl/gfx/gfx_scanout_dac.sv
@@ -2,30 +2,30 @@
module gfx_scanout_dac
(
- input logic clk,
- rst_n,
+ input logic clk,
+ rst_n,
- input logic enable_clear,
- input rgb24 clear_color,
+ input logic enable_clear,
+ input rgb24 clear_color,
- input logic mask_fifo_out,
- input mem_word fb_fifo_out,
- input logic in_valid,
- output logic in_ready,
+ input logic mask_fifo_out,
+ input vram_word fb_fifo_out,
+ input logic in_valid,
+ output logic in_ready,
- input logic scan_ready,
- output logic scan_valid,
- scan_endofpacket,
- scan_startofpacket,
- output rgb30 scan_data,
+ input logic scan_ready,
+ output logic scan_valid,
+ scan_endofpacket,
+ scan_startofpacket,
+ output rgb30 scan_data,
- output logic vsync
+ output logic vsync
);
logic dac_valid, half, half_mask, stall, endofpacket, startofpacket;
rgb24 pixel;
rgb32 fifo_pixel;
- mem_word msw, lsw;
+ vram_word msw, lsw;
half_coord next_addr;
linear_coord max_addr, pixel_addr;
@@ -42,17 +42,14 @@ module gfx_scanout_dac
assign max_addr = `GFX_X_RES * `GFX_Y_RES - 1;
- function color10 dac_color(color8 in);
- dac_color = {in, {2{in[0]}}};
- endfunction
-
assign fifo_pixel = {msw, lsw};
- assign skid_in.pixel.r = dac_color(pixel.r);
- assign skid_in.pixel.g = dac_color(pixel.g);
- assign skid_in.pixel.b = dac_color(pixel.b);
assign skid_in.endofpacket = endofpacket;
assign skid_in.startofpacket = startofpacket;
+ function color10 dac_color(color8 in);
+ dac_color = {in, {2{in[0]}}};
+ endfunction
+
always_comb begin
// Descarta fifo_pixel.a
pixel.r = fifo_pixel.r;
@@ -61,6 +58,13 @@ module gfx_scanout_dac
if (!half_mask)
pixel = clear_color;
+
+ /* Esto no puede ir en assigns. Funciona en Verilator pero causa ub en
+ * la netlist de Quartus. Eso no está documentado y perdí muchas horas.
+ */
+ skid_in.pixel.r = dac_color(pixel.r);
+ skid_in.pixel.g = dac_color(pixel.g);
+ skid_in.pixel.b = dac_color(pixel.b);
end
gfx_skid_flow flow
diff --git a/rtl/top/test_fb.sv b/rtl/top/test_fb.sv
index f784342..dba1221 100644
--- a/rtl/top/test_fb.sv
+++ b/rtl/top/test_fb.sv
@@ -1,27 +1,29 @@
+`include "gfx/gfx_defs.sv"
+
module test_fb
(
- input logic clk,
- rst_n,
+ input logic clk,
+ rst_n,
- input logic[5:0] cmd_address,
- input logic cmd_read,
- cmd_write,
- input logic[31:0] cmd_writedata,
- output logic[31:0] cmd_readdata,
+ input logic[5:0] cmd_address,
+ input logic cmd_read,
+ cmd_write,
+ input logic[31:0] cmd_writedata,
+ output logic[31:0] cmd_readdata,
- input logic mem_waitrequest,
- mem_readdatavalid,
- input logic[15:0] mem_readdata,
- output logic[25:0] mem_address,
- output logic mem_read,
- mem_write,
- output logic[15:0] mem_writedata,
+ input logic mem_waitrequest,
+ mem_readdatavalid,
+ input vram_word mem_readdata,
+ output vram_byte_addr mem_address,
+ output logic mem_read,
+ mem_write,
+ output vram_word mem_writedata,
- input logic scan_ready,
- output logic scan_valid,
- scan_endofpacket,
- scan_startofpacket,
- output logic[29:0] scan_data
+ input logic scan_ready,
+ output logic scan_valid,
+ scan_endofpacket,
+ scan_startofpacket,
+ output rgb30 scan_data
);
gfx dut
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 07:21:49 +0000