diff options
| -rw-r--r-- | conspiracion.qsf | 3 | ||||
| -rw-r--r-- | core_hw.tcl | 30 | ||||
| -rw-r--r-- | platform.qsys | 116 | ||||
| -rw-r--r-- | rtl/debounce.sv | 5 | ||||
| -rw-r--r-- | rtl/smp/pe.sv (renamed from rtl/mp/pe.sv) | 0 | ||||
| -rw-r--r-- | rtl/smp/smp_ctrl.sv (renamed from rtl/mp/mp_ctrl.sv) | 13 | ||||
| -rw-r--r-- | rtl/top/conspiracion.sv | 28 | ||||
| -rw-r--r-- | smp_hw.tcl | 190 | ||||
| -rw-r--r-- | tb/platform.sv | 2 |
9 files changed, 337 insertions, 50 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf index c833c4b..8a8ff81 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -109,7 +109,6 @@ set_global_assignment -name ECO_REGENERATE_REPORT ON set_location_assignment PIN_AF14 -to clk_clk set_location_assignment PIN_AB12 -to rst_n -set_location_assignment PIN_AC12 -to halt set_location_assignment PIN_V16 -to pio_leds[0] set_location_assignment PIN_W16 -to pio_leds[1] @@ -316,4 +315,6 @@ set_global_assignment -name SIGNALTAP_FILE bus_test.stp set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation + + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/core_hw.tcl b/core_hw.tcl index 93b6def..50d9f62 100644 --- a/core_hw.tcl +++ b/core_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Tue Sep 26 02:59:33 GMT 2023 +# Sat Sep 30 05:49:44 GMT 2023 # DO NOT MODIFY # # core "ARM810 CPU" v1.0 -# 2023.09.26.02:59:33 +# 2023.09.30.05:49:43 # # @@ -200,19 +200,19 @@ add_interface_port reset_sink rst_n reset_n Input 1 # -# connection point mp +# connection point smp # -add_interface mp conduit end -set_interface_property mp associatedClock clock_sink -set_interface_property mp associatedReset reset_sink -set_interface_property mp ENABLED true -set_interface_property mp EXPORT_OF "" -set_interface_property mp PORT_NAME_MAP "" -set_interface_property mp CMSIS_SVD_VARIABLES "" -set_interface_property mp SVD_ADDRESS_GROUP "" +add_interface smp conduit end +set_interface_property smp associatedClock clock_sink +set_interface_property smp associatedReset reset_sink +set_interface_property smp ENABLED true +set_interface_property smp EXPORT_OF "" +set_interface_property smp PORT_NAME_MAP "" +set_interface_property smp CMSIS_SVD_VARIABLES "" +set_interface_property smp SVD_ADDRESS_GROUP "" -add_interface_port mp step step Input 1 -add_interface_port mp cpu_halt cpu_halt Input 1 -add_interface_port mp cpu_halted cpu_halted Output 1 -add_interface_port mp breakpoint breakpoint Output 1 +add_interface_port smp step step Input 1 +add_interface_port smp cpu_halt halt Input 1 +add_interface_port smp cpu_halted cpu_halted Output 1 +add_interface_port smp breakpoint breakpoint Output 1 diff --git a/platform.qsys b/platform.qsys index b66adb2..7190777 100644 --- a/platform.qsys +++ b/platform.qsys @@ -206,6 +206,22 @@ type = "String"; } } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } element pll_0 { datum _sortIndex @@ -214,6 +230,14 @@ type = "int"; } } + element smp_0 + { + datum _sortIndex + { + value = "27"; + type = "int"; + } + } element switches { datum _sortIndex @@ -294,7 +318,6 @@ type="conduit" dir="end" /> <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" /> - <interface name="cpu_0_mp" internal="cpu_0.mp" type="conduit" dir="end" /> <interface name="cpu_0_mp_1" internal="cpu_0.mp_1" /> <interface name="memory" internal="hps_0.memory" type="conduit" dir="end" /> <interface @@ -370,13 +393,13 @@ <module name="cpu_0" kind="core" version="1.0" enabled="1"> <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="1" /> </module> - <module name="cpu_1" kind="core" version="1.0" enabled="0"> + <module name="cpu_1" kind="core" version="1.0" enabled="1"> <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" /> </module> - <module name="cpu_2" kind="core" version="1.0" enabled="0"> + <module name="cpu_2" kind="core" version="1.0" enabled="1"> <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" /> </module> - <module name="cpu_3" kind="core" version="1.0" enabled="0"> + <module name="cpu_3" kind="core" version="1.0" enabled="1"> <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="0" /> </module> <module name="hps_0" kind="altera_hps" version="20.1" enabled="1"> @@ -1217,6 +1240,7 @@ <parameter name="gui_switchover_mode">Automatic Switchover</parameter> <parameter name="gui_use_locked" value="false" /> </module> + <module name="smp_0" kind="smp" version="1.0" enabled="1" /> <module name="switches" kind="altera_avalon_pio" version="20.1" enabled="1"> <parameter name="bitClearingEdgeCapReg" value="false" /> <parameter name="bitModifyingOutReg" value="false" /> @@ -1370,6 +1394,11 @@ <parameter name="baseAddress" value="0x30070000" /> <parameter name="defaultConnection" value="false" /> </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="smp_0.avl"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30140000" /> + <parameter name="defaultConnection" value="false" /> + </connection> <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="buttons.s1"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30050000" /> @@ -1409,6 +1438,21 @@ <parameter name="baseAddress" value="0x0000" /> <parameter name="defaultConnection" value="false" /> </connection> + <connection kind="avalon" version="20.1" start="cpu_3.master" end="cache_3.core"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="cpu_2.master" end="cache_2.core"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="cpu_1.master" end="cache_1.core"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> <connection kind="avalon" version="20.1" @@ -1530,6 +1574,7 @@ start="pll_0.outclk0" end="hps_0.f2h_sdram0_clock" /> <connection kind="clock" version="20.1" start="pll_0.outclk1" end="mm_bridge.clk" /> + <connection kind="clock" version="20.1" start="pll_0.outclk1" end="smp_0.clock" /> <connection kind="clock" version="20.1" @@ -1558,6 +1603,21 @@ <connection kind="clock" version="20.1" + start="pll_0.outclk1" + end="cpu_3.clock_sink" /> + <connection + kind="clock" + version="20.1" + start="pll_0.outclk1" + end="cpu_2.clock_sink" /> + <connection + kind="clock" + version="20.1" + start="pll_0.outclk1" + end="cpu_1.clock_sink" /> + <connection + kind="clock" + version="20.1" start="sys_sdram_pll_0.sys_clk" end="vram.clk" /> <connection @@ -1581,6 +1641,34 @@ version="20.1" start="video_pll_0.vga_clk" end="pixfifo.clock_stream_out" /> + <connection kind="conduit" version="20.1" start="cpu_0.smp" end="smp_0.cpu_0"> + <parameter name="endPort" value="" /> + <parameter name="endPortLSB" value="0" /> + <parameter name="startPort" value="" /> + <parameter name="startPortLSB" value="0" /> + <parameter name="width" value="0" /> + </connection> + <connection kind="conduit" version="20.1" start="cpu_1.smp" end="smp_0.cpu_1"> + <parameter name="endPort" value="" /> + <parameter name="endPortLSB" value="0" /> + <parameter name="startPort" value="" /> + <parameter name="startPortLSB" value="0" /> + <parameter name="width" value="0" /> + </connection> + <connection kind="conduit" version="20.1" start="cpu_2.smp" end="smp_0.cpu_2"> + <parameter name="endPort" value="" /> + <parameter name="endPortLSB" value="0" /> + <parameter name="startPort" value="" /> + <parameter name="startPortLSB" value="0" /> + <parameter name="width" value="0" /> + </connection> + <connection kind="conduit" version="20.1" start="cpu_3.smp" end="smp_0.cpu_3"> + <parameter name="endPort" value="" /> + <parameter name="endPortLSB" value="0" /> + <parameter name="startPort" value="" /> + <parameter name="startPortLSB" value="0" /> + <parameter name="width" value="0" /> + </connection> <connection kind="interrupt" version="20.1" @@ -1681,6 +1769,26 @@ <connection kind="reset" version="20.1" + start="clk_0.clk_reset" + end="cpu_3.reset_sink" /> + <connection + kind="reset" + version="20.1" + start="clk_0.clk_reset" + end="cpu_2.reset_sink" /> + <connection + kind="reset" + version="20.1" + start="clk_0.clk_reset" + end="cpu_1.reset_sink" /> + <connection + kind="reset" + version="20.1" + start="clk_0.clk_reset" + end="smp_0.reset_sink" /> + <connection + kind="reset" + version="20.1" start="sys_sdram_pll_0.reset_source" end="vram.reset" /> <connection diff --git a/rtl/debounce.sv b/rtl/debounce.sv index 919588a..434d056 100644 --- a/rtl/debounce.sv +++ b/rtl/debounce.sv @@ -2,13 +2,14 @@ module debounce ( input logic clk, dirty, + output logic clean ); logic last; - // 168ms para reloj de 50MHz - logic[22:0] clean_for; + // 671ms para reloj de 50MHz + logic[24:0] clean_for; always @(posedge clk) begin last <= dirty; diff --git a/rtl/mp/pe.sv b/rtl/smp/pe.sv index f50ed2f..f50ed2f 100644 --- a/rtl/mp/pe.sv +++ b/rtl/smp/pe.sv diff --git a/rtl/mp/mp_ctrl.sv b/rtl/smp/smp_ctrl.sv index 362e450..b6123ad 100644 --- a/rtl/mp/mp_ctrl.sv +++ b/rtl/smp/smp_ctrl.sv @@ -1,4 +1,4 @@ -module mp_ctrl +module smp_ctrl ( input logic clk, rst_n, @@ -37,6 +37,17 @@ module mp_ctrl // No hay addresses assign write = avl_write; + mp_pe #(.IS_BSP(1)) pe_0 + ( + .step(step_0), + .halt(halt_0), + .cpu_halted(cpu_halted_0), + .breakpoint(breakpoint_0), + .readdata(readdata_0), + .writedata(writedata_0), + .* + ); + mp_pe pe_1 ( .step(step_1), diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 54c8b95..9467cd7 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -3,13 +3,6 @@ module conspiracion input wire clk_clk, input wire rst_n, - input wire halt, -`ifdef VERILATOR - input wire step, - output wire breakpoint, -`endif - output wire cpu_halted, - output wire [12:0] memory_mem_a, output wire [2:0] memory_mem_ba, output wire memory_mem_ck, @@ -49,10 +42,9 @@ module conspiracion output wire [7:0] vga_dac_b ); - logic button, cpu_halt, reset_reset_n; + logic button, reset_reset_n; `ifdef VERILATOR - assign cpu_halt = halt; assign reset_reset_n = rst_n; assign button = pio_buttons; `else @@ -63,13 +55,6 @@ module conspiracion .clean(reset_reset_n) ); - debounce halt_debounce - ( - .clk(cpu_clk), - .dirty(halt), - .clean(cpu_halt) - ); - debounce button_debounce ( .clk(clk_clk), @@ -80,19 +65,10 @@ module conspiracion platform plat ( -`ifdef VERILATOR - .cpu_0_mp_step(step), - .cpu_0_mp_breakpoint(breakpoint), -`else - .cpu_0_mp_step(0), - .cpu_0_mp_breakpoint(), -`endif - .cpu_0_mp_cpu_halt(cpu_halt), - .cpu_0_mp_cpu_halted(cpu_halted), .pll_0_reset_reset(0), //TODO: reset controller, algún día .pio_0_external_connection_export(pio_leds), .switches_external_connection_export({2'b00, pio_switches}), - //TODO: glitch rst + //FIXME: el glitch de reset .buttons_external_connection_export({7'b0000000, !button}), .sys_sdram_pll_0_sdram_clk_clk(vram_wire_clk), .vga_dac_CLK(vga_dac_clk), diff --git a/smp_hw.tcl b/smp_hw.tcl new file mode 100644 index 0000000..f96039e --- /dev/null +++ b/smp_hw.tcl @@ -0,0 +1,190 @@ +# TCL File Generated by Component Editor 20.1 +# Sat Sep 30 05:54:51 GMT 2023 +# DO NOT MODIFY + + +# +# smp "SMP controller" v1.0 +# 2023.09.30.05:54:51 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module smp +# +set_module_property DESCRIPTION "" +set_module_property NAME smp +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME "SMP controller" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL smp_ctrl +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file smp_ctrl.sv SYSTEM_VERILOG PATH rtl/smp/smp_ctrl.sv TOP_LEVEL_FILE +add_fileset_file pe.sv SYSTEM_VERILOG PATH rtl/smp/pe.sv + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point avl +# +add_interface avl avalon end +set_interface_property avl addressUnits WORDS +set_interface_property avl associatedClock clock +set_interface_property avl associatedReset reset_sink +set_interface_property avl bitsPerSymbol 8 +set_interface_property avl burstOnBurstBoundariesOnly false +set_interface_property avl burstcountUnits WORDS +set_interface_property avl explicitAddressSpan 0 +set_interface_property avl holdTime 0 +set_interface_property avl linewrapBursts false +set_interface_property avl maximumPendingReadTransactions 0 +set_interface_property avl maximumPendingWriteTransactions 0 +set_interface_property avl readLatency 0 +set_interface_property avl readWaitTime 1 +set_interface_property avl setupTime 0 +set_interface_property avl timingUnits Cycles +set_interface_property avl writeWaitTime 0 +set_interface_property avl ENABLED true +set_interface_property avl EXPORT_OF "" +set_interface_property avl PORT_NAME_MAP "" +set_interface_property avl CMSIS_SVD_VARIABLES "" +set_interface_property avl SVD_ADDRESS_GROUP "" + +add_interface_port avl avl_read read Input 1 +add_interface_port avl avl_write write Input 1 +add_interface_port avl avl_writedata writedata Input 32 +add_interface_port avl avl_readdata readdata Output 32 +set_interface_assignment avl embeddedsw.configuration.isFlash 0 +set_interface_assignment avl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point reset_sink +# +add_interface reset_sink reset end +set_interface_property reset_sink associatedClock clock +set_interface_property reset_sink synchronousEdges DEASSERT +set_interface_property reset_sink ENABLED true +set_interface_property reset_sink EXPORT_OF "" +set_interface_property reset_sink PORT_NAME_MAP "" +set_interface_property reset_sink CMSIS_SVD_VARIABLES "" +set_interface_property reset_sink SVD_ADDRESS_GROUP "" + +add_interface_port reset_sink rst_n reset_n Input 1 + + +# +# connection point cpu_0 +# +add_interface cpu_0 conduit end +set_interface_property cpu_0 associatedClock clock +set_interface_property cpu_0 associatedReset reset_sink +set_interface_property cpu_0 ENABLED true +set_interface_property cpu_0 EXPORT_OF "" +set_interface_property cpu_0 PORT_NAME_MAP "" +set_interface_property cpu_0 CMSIS_SVD_VARIABLES "" +set_interface_property cpu_0 SVD_ADDRESS_GROUP "" + +add_interface_port cpu_0 halt_0 halt Output 1 +add_interface_port cpu_0 step_0 step Output 1 +add_interface_port cpu_0 cpu_halted_0 cpu_halted Input 1 +add_interface_port cpu_0 breakpoint_0 breakpoint Input 1 + + +# +# connection point cpu_1 +# +add_interface cpu_1 conduit end +set_interface_property cpu_1 associatedClock clock +set_interface_property cpu_1 associatedReset reset_sink +set_interface_property cpu_1 ENABLED true +set_interface_property cpu_1 EXPORT_OF "" +set_interface_property cpu_1 PORT_NAME_MAP "" +set_interface_property cpu_1 CMSIS_SVD_VARIABLES "" +set_interface_property cpu_1 SVD_ADDRESS_GROUP "" + +add_interface_port cpu_1 breakpoint_1 breakpoint Input 1 +add_interface_port cpu_1 cpu_halted_1 cpu_halted Input 1 +add_interface_port cpu_1 halt_1 halt Output 1 +add_interface_port cpu_1 step_1 step Output 1 + + +# +# connection point cpu_2 +# +add_interface cpu_2 conduit end +set_interface_property cpu_2 associatedClock clock +set_interface_property cpu_2 associatedReset reset_sink +set_interface_property cpu_2 ENABLED true +set_interface_property cpu_2 EXPORT_OF "" +set_interface_property cpu_2 PORT_NAME_MAP "" +set_interface_property cpu_2 CMSIS_SVD_VARIABLES "" +set_interface_property cpu_2 SVD_ADDRESS_GROUP "" + +add_interface_port cpu_2 breakpoint_2 breakpoint Input 1 +add_interface_port cpu_2 cpu_halted_2 cpu_halted Input 1 +add_interface_port cpu_2 halt_2 halt Output 1 +add_interface_port cpu_2 step_2 step Output 1 + + +# +# connection point cpu_3 +# +add_interface cpu_3 conduit end +set_interface_property cpu_3 associatedClock clock +set_interface_property cpu_3 associatedReset reset_sink +set_interface_property cpu_3 ENABLED true +set_interface_property cpu_3 EXPORT_OF "" +set_interface_property cpu_3 PORT_NAME_MAP "" +set_interface_property cpu_3 CMSIS_SVD_VARIABLES "" +set_interface_property cpu_3 SVD_ADDRESS_GROUP "" + +add_interface_port cpu_3 breakpoint_3 breakpoint Input 1 +add_interface_port cpu_3 cpu_halted_3 cpu_halted Input 1 +add_interface_port cpu_3 halt_3 halt Output 1 +add_interface_port cpu_3 step_3 step Output 1 diff --git a/tb/platform.sv b/tb/platform.sv index 5661150..c729b56 100644 --- a/tb/platform.sv +++ b/tb/platform.sv @@ -263,7 +263,7 @@ module platform .out_token_valid(token_valid_3) ); - mp_ctrl mp + smp_ctrl smp ( .clk(), .rst_n(), |