diff options
| -rw-r--r-- | .gitignore | 1 | ||||
| -rw-r--r-- | c5_pin_model_dump.txt | 118 | ||||
| -rw-r--r-- | conspiracion.qsf | 132 | ||||
| -rwxr-xr-x | hps_sdram_p0_all_pins.txt | 42 | ||||
| -rw-r--r-- | pitfalls.txt | 18 |
5 files changed, 311 insertions, 0 deletions
@@ -37,3 +37,4 @@ obj/ .qsys_edit/ platform/ platform.sopcinfo +hps_isw_handoff/ diff --git a/c5_pin_model_dump.txt b/c5_pin_model_dump.txt new file mode 100644 index 0000000..31bb72c --- /dev/null +++ b/c5_pin_model_dump.txt @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2 +io_4iomodule_c5_index: 54gpio_index: 465 +io_4iomodule_c5_index: 33gpio_index: 6 +io_4iomodule_c5_index: 51gpio_index: 461 +io_4iomodule_c5_index: 27gpio_index: 10 +io_4iomodule_c5_index: 57gpio_index: 457 +io_4iomodule_c5_index: 34gpio_index: 14 +io_4iomodule_c5_index: 28gpio_index: 453 +io_4iomodule_c5_index: 26gpio_index: 19 +io_4iomodule_c5_index: 47gpio_index: 449 +io_4iomodule_c5_index: 29gpio_index: 22 +io_4iomodule_c5_index: 3gpio_index: 445 +io_4iomodule_c5_index: 16gpio_index: 27 +io_4iomodule_c5_index: 6gpio_index: 441 +io_4iomodule_c5_index: 50gpio_index: 30 +io_4iomodule_c5_index: 35gpio_index: 437 +io_4iomodule_c5_index: 7gpio_index: 35 +io_4iomodule_c5_index: 53gpio_index: 433 +io_4iomodule_c5_index: 12gpio_index: 38 +io_4iomodule_c5_index: 1gpio_index: 429 +io_4iomodule_c5_index: 22gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 425 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 30gpio_index: 421 +io_4iomodule_c5_index: 2gpio_index: 51 +io_4iomodule_c5_index: 31gpio_index: 417 +io_4iomodule_c5_index: 39gpio_index: 54 +io_4iomodule_c5_index: 18gpio_index: 413 +io_4iomodule_c5_index: 10gpio_index: 59 +io_4iomodule_c5_index: 42gpio_index: 409 +io_4iomodule_c5_index: 5gpio_index: 62 +io_4iomodule_c5_index: 24gpio_index: 405 +io_4iomodule_c5_index: 37gpio_index: 67 +io_4iomodule_c5_index: 13gpio_index: 401 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 44gpio_index: 397 +io_4iomodule_c5_index: 38gpio_index: 75 +io_4iomodule_c5_index: 52gpio_index: 393 +io_4iomodule_c5_index: 32gpio_index: 78 +io_4iomodule_c5_index: 56gpio_index: 389 +io_4iomodule_a_index: 13gpio_index: 385 +io_4iomodule_c5_index: 4gpio_index: 83 +io_4iomodule_c5_index: 23gpio_index: 86 +io_4iomodule_a_index: 15gpio_index: 381 +io_4iomodule_a_index: 8gpio_index: 377 +io_4iomodule_c5_index: 46gpio_index: 91 +io_4iomodule_a_index: 5gpio_index: 373 +io_4iomodule_a_index: 11gpio_index: 369 +io_4iomodule_c5_index: 41gpio_index: 94 +io_4iomodule_a_index: 3gpio_index: 365 +io_4iomodule_c5_index: 25gpio_index: 99 +io_4iomodule_a_index: 7gpio_index: 361 +io_4iomodule_c5_index: 9gpio_index: 102 +io_4iomodule_a_index: 0gpio_index: 357 +io_4iomodule_c5_index: 14gpio_index: 107 +io_4iomodule_a_index: 12gpio_index: 353 +io_4iomodule_c5_index: 45gpio_index: 110 +io_4iomodule_c5_index: 17gpio_index: 115 +io_4iomodule_a_index: 4gpio_index: 349 +io_4iomodule_c5_index: 36gpio_index: 118 +io_4iomodule_a_index: 10gpio_index: 345 +io_4iomodule_a_index: 16gpio_index: 341 +io_4iomodule_c5_index: 15gpio_index: 123 +io_4iomodule_a_index: 14gpio_index: 337 +io_4iomodule_c5_index: 43gpio_index: 126 +io_4iomodule_c5_index: 19gpio_index: 131 +io_4iomodule_a_index: 1gpio_index: 333 +io_4iomodule_c5_index: 59gpio_index: 134 +io_4iomodule_a_index: 2gpio_index: 329 +io_4iomodule_a_index: 9gpio_index: 325 +io_4iomodule_c5_index: 48gpio_index: 139 +io_4iomodule_a_index: 6gpio_index: 321 +io_4iomodule_a_index: 17gpio_index: 317 +io_4iomodule_c5_index: 40gpio_index: 142 +io_4iomodule_c5_index: 11gpio_index: 147 +io_4iomodule_c5_index: 58gpio_index: 150 +io_4iomodule_c5_index: 21gpio_index: 155 +io_4iomodule_c5_index: 49gpio_index: 158 +io_4iomodule_h_c5_index: 0gpio_index: 161 +io_4iomodule_h_c5_index: 6gpio_index: 165 +io_4iomodule_h_c5_index: 10gpio_index: 169 +io_4iomodule_h_c5_index: 3gpio_index: 173 +io_4iomodule_h_c5_index: 8gpio_index: 176 +io_4iomodule_h_c5_index: 11gpio_index: 180 +io_4iomodule_h_c5_index: 7gpio_index: 184 +io_4iomodule_h_c5_index: 5gpio_index: 188 +io_4iomodule_h_c5_index: 1gpio_index: 192 +io_4iomodule_h_c5_index: 2gpio_index: 196 +io_4iomodule_h_c5_index: 9gpio_index: 200 +io_4iomodule_h_c5_index: 4gpio_index: 204 +io_4iomodule_h_index: 15gpio_index: 208 +io_4iomodule_h_index: 1gpio_index: 212 +io_4iomodule_h_index: 3gpio_index: 216 +io_4iomodule_h_index: 2gpio_index: 220 +io_4iomodule_h_index: 11gpio_index: 224 +io_4iomodule_vref_h_index: 1gpio_index: 228 +io_4iomodule_h_index: 20gpio_index: 231 +io_4iomodule_h_index: 8gpio_index: 235 +io_4iomodule_h_index: 6gpio_index: 239 +io_4iomodule_h_index: 10gpio_index: 243 +io_4iomodule_h_index: 23gpio_index: 247 +io_4iomodule_h_index: 7gpio_index: 251 +io_4iomodule_h_index: 22gpio_index: 255 +io_4iomodule_h_index: 5gpio_index: 259 +io_4iomodule_h_index: 24gpio_index: 263 +io_4iomodule_h_index: 0gpio_index: 267 +io_4iomodule_h_index: 13gpio_index: 271 +io_4iomodule_h_index: 21gpio_index: 275 +io_4iomodule_h_index: 16gpio_index: 279 +io_4iomodule_vref_h_index: 0gpio_index: 283 +io_4iomodule_h_index: 12gpio_index: 286 +io_4iomodule_h_index: 4gpio_index: 290 +io_4iomodule_h_index: 19gpio_index: 294 +io_4iomodule_h_index: 18gpio_index: 298 +io_4iomodule_h_index: 17gpio_index: 302 +io_4iomodule_h_index: 25gpio_index: 306 +io_4iomodule_h_index: 14gpio_index: 310 +io_4iomodule_h_index: 9gpio_index: 314 diff --git a/conspiracion.qsf b/conspiracion.qsf index 2543434..0aa975f 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -58,4 +58,136 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name SYSTEMVERILOG_FILE rtl/conspiracion.sv set_global_assignment -name QIP_FILE platform/synthesis/platform.qip +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_oct_rzqin -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[3] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[4] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[5] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[6] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[7] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs_n -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_ck -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck -tag __hps_sdram_p0 +set_instance_assignment -name D5_DELAY 2 -to memory_mem_ck -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_ck_n -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck_n -tag __hps_sdram_p0 +set_instance_assignment -name D5_DELAY 2 -to memory_mem_ck_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[10] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[10] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[11] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[11] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[12] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[12] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[3] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[3] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[4] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[4] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[5] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[5] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[6] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[6] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[7] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[7] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[8] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[8] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[9] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[9] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cas_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cas_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cke -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cke -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cs_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cs_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_odt -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_odt -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ras_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ras_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_we_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_we_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dm -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dm -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[10] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[11] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[12] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[8] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[9] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cas_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cke -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cs_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_odt -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ras_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_we_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ck -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ck_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0 +set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to plat|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0 +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to plat|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0 +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON +set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name ECO_REGENERATE_REPORT ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/hps_sdram_p0_all_pins.txt b/hps_sdram_p0_all_pins.txt new file mode 100755 index 0000000..70f45e1 --- /dev/null +++ b/hps_sdram_p0_all_pins.txt @@ -0,0 +1,42 @@ +# PIN MAP for core < hps_sdram_p0 > +# +# Generated by hps_sdram_p0_pin_assignments.tcl +# +# This file is for reference only and is not used by Quartus Prime +# + +INSTANCE: plat|hps_0|hps_io|border|hps_sdram_inst +DQS: memory_mem_dqs +DQSn: memory_mem_dqs_n +DQ: {{memory_mem_dq[0]} {memory_mem_dq[1]} {memory_mem_dq[2]} {memory_mem_dq[3]} {memory_mem_dq[4]} {memory_mem_dq[5]} {memory_mem_dq[6]} {memory_mem_dq[7]}} +DM memory_mem_dm +CK: memory_mem_ck +CKn: memory_mem_ck_n +ADD: {memory_mem_a[0]} {memory_mem_a[10]} {memory_mem_a[11]} {memory_mem_a[12]} {memory_mem_a[1]} {memory_mem_a[2]} {memory_mem_a[3]} {memory_mem_a[4]} {memory_mem_a[5]} {memory_mem_a[6]} {memory_mem_a[7]} {memory_mem_a[8]} {memory_mem_a[9]} +CMD: memory_mem_cas_n memory_mem_cke memory_mem_cs_n memory_mem_odt memory_mem_ras_n memory_mem_we_n +RESET: memory_mem_reset_n +BA: {memory_mem_ba[0]} {memory_mem_ba[1]} {memory_mem_ba[2]} +PLL CK: platform:plat|platform_hps_0:hps_0|platform_hps_0_hps_io:hps_io|platform_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk +PLL DQ WRITE: platform:plat|platform_hps_0:hps_0|platform_hps_0_hps_io:hps_io|platform_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk +PLL WRITE: platform:plat|platform_hps_0:hps_0|platform_hps_0_hps_io:hps_io|platform_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk +PLL DRIVER CORE: _UNDEFINED_PIN_ +DQS_IN_CLOCK DQS_PIN (0): memory_mem_dqs +DQS_IN_CLOCK DQS_SHIFTED_PIN (0): plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout +DQS_IN_CLOCK DIV_NAME (0): plat|hps_0|hps_io|border|hps_sdram_inst|div_clock_0 +DQS_IN_CLOCK DIV_PIN (0): plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0] +DQS_OUT_CLOCK SRC (0): plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o +DQS_OUT_CLOCK DST (0): memory_mem_dqs +DQS_OUT_CLOCK DM (0): memory_mem_dm +DQSN_OUT_CLOCK SRC (0): plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o +DQSN_OUT_CLOCK DST (0): memory_mem_dqs_n +DQSN_OUT_CLOCK DM (0): memory_mem_dm +READ CAPTURE DDIO: {*:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]} +AFI RESET REGISTERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:ureset|*:ureset_afi_clk|reset_reg[3] +SYNCHRONIZERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].seq_read_fifo_reset_sync +SYNCHRONIZATION FIFO WRITE ADDRESS REGISTERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*] +SYNCHRONIZATION FIFO WRITE REGISTERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|*INPUT_DFF* +SYNCHRONIZATION FIFO READ REGISTERS: *:plat|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|dout[*] + +# +# END OF INSTANCE: plat|hps_0|hps_io|border|hps_sdram_inst + diff --git a/pitfalls.txt b/pitfalls.txt new file mode 100644 index 0000000..9cca2c2 --- /dev/null +++ b/pitfalls.txt @@ -0,0 +1,18 @@ + === + [I] Setup del HPS y SDRAM + === + +Luego de agregar el HPS a Platform Designer hay que ejecutar un script Tcl para +que Quartus agarre la config correcta de impedancias y más magia. Si se +sintetiza sin más acción entonces pasa esto: + + Error (174068): Output buffer atom "platform:plat|platform_hps_0:hps_0|platform_hps_0_hps_io:hps_io|platform_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|obuf_os_bar_0" has port "PARALLELTERMINATIONCONTROL[8]" connected, but does not use calibrated on-chip termination + +Foro: <https://community.intel.com/t5/Programmable-Devices/Build-HPS-Hardware/td-p/219711> + +Tools > Tcl Scripts. There navigate through your QSys project, synthesis > +submodules folders, and there you should find a script whose name ends with +pin_assignments.tcl . Select that script, run it and try and compile the +project again + +Nota: es *_pin_assignments.tcl y no ningún otro |