diff options
| -rw-r--r-- | gfx_hw.tcl | 43 | ||||
| -rw-r--r-- | platform.qsys | 5 | ||||
| -rw-r--r-- | rtl/gfx/gfx.sv | 8 | ||||
| -rw-r--r-- | rtl/gfx/gfx_defs.sv | 6 | ||||
| -rw-r--r-- | rtl/gfx/gfx_mem.sv | 32 | ||||
| -rw-r--r-- | rtl/top/test_fb.sv | 14 |
6 files changed, 97 insertions, 11 deletions
@@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Sat Oct 28 21:45:46 GMT 2023 +# Mon Nov 20 21:56:17 GMT 2023 # DO NOT MODIFY # # gfx "3D graphics accelerator" v1.0 -# 2023.10.28.21:45:46 +# 2023.11.20.21:56:17 # # @@ -222,3 +222,42 @@ add_interface_port scan scan_ready ready Input 1 add_interface_port scan scan_startofpacket startofpacket Output 1 add_interface_port scan scan_valid valid Output 1 + +# +# connection point host +# +add_interface host avalon end +set_interface_property host addressUnits WORDS +set_interface_property host associatedClock clock +set_interface_property host associatedReset reset_sink +set_interface_property host bitsPerSymbol 8 +set_interface_property host burstOnBurstBoundariesOnly false +set_interface_property host burstcountUnits WORDS +set_interface_property host explicitAddressSpan 0 +set_interface_property host holdTime 0 +set_interface_property host linewrapBursts false +set_interface_property host maximumPendingReadTransactions 13 +set_interface_property host maximumPendingWriteTransactions 0 +set_interface_property host readLatency 0 +set_interface_property host readWaitTime 1 +set_interface_property host setupTime 0 +set_interface_property host timingUnits Cycles +set_interface_property host writeWaitTime 0 +set_interface_property host ENABLED true +set_interface_property host EXPORT_OF "" +set_interface_property host PORT_NAME_MAP "" +set_interface_property host CMSIS_SVD_VARIABLES "" +set_interface_property host SVD_ADDRESS_GROUP "" + +add_interface_port host host_address address Input 25 +add_interface_port host host_read read Input 1 +add_interface_port host host_write write Input 1 +add_interface_port host host_readdata readdata Output 16 +add_interface_port host host_writedata writedata Input 16 +add_interface_port host host_readdatavalid readdatavalid Output 1 +add_interface_port host host_waitrequest waitrequest Output 1 +set_interface_assignment host embeddedsw.configuration.isFlash 0 +set_interface_assignment host embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment host embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment host embeddedsw.configuration.isPrintableDevice 0 + diff --git a/platform.qsys b/platform.qsys index e795efe..f8704a6 100644 --- a/platform.qsys +++ b/platform.qsys @@ -1405,6 +1405,11 @@ <parameter name="baseAddress" value="0x30130000" /> <parameter name="defaultConnection" value="false" /> </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="gfx_0.host"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x38000000" /> + <parameter name="defaultConnection" value="false" /> + </connection> <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="perf_0.perf"> <parameter name="arbitrationPriority" value="1" /> <parameter name="baseAddress" value="0x30150000" /> diff --git a/rtl/gfx/gfx.sv b/rtl/gfx/gfx.sv index 1da3550..4837b8e 100644 --- a/rtl/gfx/gfx.sv +++ b/rtl/gfx/gfx.sv @@ -19,6 +19,14 @@ module gfx mem_write, output vram_word mem_writedata, + input vram_addr host_address, + input logic host_read, + host_write, + input vram_word host_writedata, + output logic host_waitrequest, + host_readdatavalid, + output vram_word host_readdata, + input logic scan_ready, output logic scan_valid, scan_endofpacket, diff --git a/rtl/gfx/gfx_defs.sv b/rtl/gfx/gfx_defs.sv index 86fa21a..20102a4 100644 --- a/rtl/gfx/gfx_defs.sv +++ b/rtl/gfx/gfx_defs.sv @@ -162,9 +162,13 @@ typedef struct packed `define GFX_MEM_SUBWORD_BITS ($clog2(`GFX_MEM_DATA_BITS / 8)) `define GFX_MEM_ADDR_BITS (`GFX_MEM_WORD_ADDR_BITS + `GFX_MEM_SUBWORD_BITS) `define GFX_MEM_RESPONSE_DEPTH 2 // Ajustar -`define GFX_MEM_TRANS_DEPTH 4 // Ajustar +`define GFX_MEM_TRANS_DEPTH 4 // NO TOCAR, ver `GFX_MEM_MAX_PENDING_READS `define GFX_MEM_DISPATCH_DEPTH 8 // Nótese que platform.vram_0.s1.maximumPendingReadTransactions = 7 +// NO TOCAR. Esto debe coincidir perfectamente con gfx_hw.tcl +`define GFX_VRAM_MAX_PENDING_READS 7 // platform.vram_0.s1.maximumPendingReadTransactions +`define GFX_MEM_MAX_PENDING_READS (1 + `GFX_MEM_TRANS_DEPTH + 1 + `GFX_VRAM_MAX_PENDING_READS) + typedef logic[`GFX_MEM_DATA_BITS - 1:0] vram_word; typedef logic[`GFX_MEM_ADDR_BITS - 1:0] vram_byte_addr; typedef logic[`GFX_MEM_WORD_ADDR_BITS - 1:0] vram_addr; diff --git a/rtl/gfx/gfx_mem.sv b/rtl/gfx/gfx_mem.sv index c4e9146..0176858 100644 --- a/rtl/gfx/gfx_mem.sv +++ b/rtl/gfx/gfx_mem.sv @@ -13,6 +13,14 @@ module gfx_mem mem_write, output vram_word mem_writedata, + input vram_addr host_address, + input logic host_read, + host_write, + input vram_word host_writedata, + output logic host_waitrequest, + host_readdatavalid, + output vram_word host_readdata, + input logic rop_write, input vram_word rop_writedata, input half_coord rop_address, @@ -39,7 +47,7 @@ module gfx_mem // Este módulo es inaceptable, hay que reescribirlo - logic mem_rw, trans_in_stall, trans_out_stall, in_ready, skid_in_valid, out_ready, + logic mem_rw, trans_in_stall, trans_out_stall, in_ready, in_valid, skid_in_valid, out_ready, any_readdatavalid, readdatavalid, dispatch_full, dispatch_put, mem_ready; vram_word any_readdata, readdata; @@ -48,6 +56,7 @@ module gfx_mem struct packed { logic fb, + host, batch, fetch; } dispatch_in, dispatch_out, dispatch_buf[`GFX_MEM_DISPATCH_DEPTH]; @@ -57,6 +66,7 @@ module gfx_mem vram_addr address; logic write, fb_waitrequest, + host_waitrequest, batch_waitrequest, fetch_waitrequest; vram_word writedata; @@ -68,17 +78,21 @@ module gfx_mem assign mem_writedata = trans_out_skid.writedata; assign fb_readdata = any_readdata; + assign host_readdata = any_readdata; assign batch_readdata = any_readdata; assign fetch_readdata = any_readdata; assign fb_readdatavalid = any_readdatavalid && dispatch_out.fb; + assign host_readdatavalid = any_readdatavalid && dispatch_out.host; assign batch_readdatavalid = any_readdatavalid && dispatch_out.batch; assign fetch_readdatavalid = any_readdatavalid && dispatch_out.fetch; assign dispatch_in.fb = !trans_out_skid.fb_waitrequest; + assign dispatch_in.host = !trans_out_skid.host_waitrequest; assign dispatch_in.batch = !trans_out_skid.batch_waitrequest; assign dispatch_in.fetch = !trans_out_skid.fetch_waitrequest; + assign in_valid = rop_write || fb_read || batch_read || fetch_read || host_read || host_write; assign mem_ready = !mem_waitrequest && (!dispatch_full || trans_out_skid.write); assign next_put_ptr = put_ptr + 1; assign dispatch_put = mem_ready && mem_rw && !trans_out_skid.write; @@ -100,8 +114,6 @@ module gfx_mem gfx_skid_flow in_flow ( .stall(trans_in_stall), - .in_ready(in_ready), - .in_valid(rop_write || fb_read || batch_read || fetch_read), .out_ready(out_ready), .out_valid(skid_in_valid), .* @@ -154,11 +166,12 @@ module gfx_mem always_comb begin fb_waitrequest = 1; rop_waitrequest = 1; + host_waitrequest = 1; batch_waitrequest = 1; fetch_waitrequest = 1; trans_in.write = 0; - trans_in.writedata = rop_writedata; + trans_in.writedata = {($bits(trans_in.writedata)){1'bx}}; if (fb_read) begin fb_waitrequest = !in_ready; @@ -168,14 +181,23 @@ module gfx_mem trans_in.address = batch_address; end else if (rop_write) begin rop_waitrequest = !in_ready; + trans_in.write = 1; trans_in.address = {5'd0, rop_address}; - end else begin + trans_in.writedata = rop_writedata; + end else if (fetch_read) begin fetch_waitrequest = !in_ready; trans_in.address = fetch_address; + end else begin + host_waitrequest = !in_ready; + + trans_in.write = host_write; + trans_in.address = host_address; + trans_in.writedata = host_writedata; end trans_in.fb_waitrequest = fb_waitrequest; + trans_in.host_waitrequest = host_waitrequest; trans_in.batch_waitrequest = batch_waitrequest; trans_in.fetch_waitrequest = fetch_waitrequest; end diff --git a/rtl/top/test_fb.sv b/rtl/top/test_fb.sv index dba1221..d43f252 100644 --- a/rtl/top/test_fb.sv +++ b/rtl/top/test_fb.sv @@ -5,11 +5,11 @@ module test_fb input logic clk, rst_n, - input logic[5:0] cmd_address, + input cmd_addr cmd_address, input logic cmd_read, cmd_write, - input logic[31:0] cmd_writedata, - output logic[31:0] cmd_readdata, + input cmd_word cmd_writedata, + output cmd_word cmd_readdata, input logic mem_waitrequest, mem_readdatavalid, @@ -19,6 +19,14 @@ module test_fb mem_write, output vram_word mem_writedata, + input vram_addr host_address, + input logic host_read, + host_write, + input vram_word host_writedata, + output logic host_waitrequest, + host_readdatavalid, + output vram_word host_readdata, + input logic scan_ready, output logic scan_valid, scan_endofpacket, |