diff options
| -rw-r--r-- | rtl/core/control/control.sv | 21 | ||||
| -rw-r--r-- | rtl/core/control/writeback.sv | 26 |
2 files changed, 29 insertions, 18 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index fa4510c..ec8f773 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -54,7 +54,7 @@ module core_control coproc ); - logic final_update_flags, ldst, ldst_pre, ldst_increment, + logic ldst, ldst_pre, ldst_increment, ldst_writeback, pop_valid, exception, high_vectors; logic[2:0] vector_offset; @@ -114,7 +114,7 @@ module core_control .* ); - logic final_writeback; + logic final_writeback, final_update_flags; reg_num final_rd; core_control_writeback ctrl_wb @@ -126,13 +126,10 @@ module core_control vector_offset = 3'b001; //TODO always_ff @(posedge clk) begin - update_flags <= 0; wb_alu_flags <= alu_flags; unique case(next_cycle) - ISSUE: begin - final_update_flags <= 0; - + ISSUE: if(issue) begin ra <= dec_data.rn; rb <= dec_snd.r; @@ -154,13 +151,8 @@ module core_control mem_regs <= dec_ldst.regs; mem_write <= !dec_ldst.load; - - final_update_flags <= dec.update_flags; end - update_flags <= final_update_flags; - end - RD_INDIRECT_SHIFT: rb <= r_shift; @@ -187,12 +179,7 @@ module core_control BASE_WRITEBACK: ; - EXCEPTION: - //TODO: spsr_<mode> = cpsr - //TODO: actualizar modo - //TODO: deshabilitar IRQs/FIQs dependiendo de modo - //TODO: Considerar que data abort usa + 8, no + 4 - final_update_flags <= 0; + EXCEPTION: ; endcase end diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 2ba0845..021d494 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -24,6 +24,8 @@ module core_control_writeback final_rd, output logic writeback, final_writeback, + update_flags, + final_update_flags, output word wr_value ); @@ -85,6 +87,23 @@ module core_control_writeback default: wr_value <= q_alu; endcase + update_flags <= 0; + unique0 case(next_cycle) + ISSUE: + update_flags <= final_update_flags; + + EXCEPTION: + final_update_flags <= 0; + endcase + + unique0 case(next_cycle) + ISSUE: + final_update_flags <= issue && dec.update_flags; + + EXCEPTION: + final_update_flags <= 0; + endcase + unique0 case(next_cycle) TRANSFER: if(mem_ready) @@ -101,9 +120,14 @@ module core_control_writeback initial begin rd = 0; final_rd = 0; - wr_value = 0; + writeback = 0; final_writeback = 0; + + update_flags = 0; + final_update_flags = 0; + + wr_value = 0; end endmodule |